Synthesis

[rosalba_zarate]

Hello everybody,

I am using verilog Xilinx ISE 13.2 (nt64), under xc5vfx100t-2ff1738. 

I have been searching but I can't understand why when I synthesize (SYNTHESIZE-XST) I have different logic utilization available for two different designs (second design used BRAMs compared to the first one that used many registers). I thought the logic utilization available wouldn't change in both designs, so I could be able to compare both designs. 

My questions:

1. Why do I have different logic utilization? Is this normal? Should the logic utilization available be static with any design or FPGA searches to fit in different ways?

2. Which project do you think spend less resources? This is needed because my module will be part of a big module with other some modules, so I need to economize the most.

Device Utilization (HW)	1st Design Freq. 83.425MHz			2nd Design Freq. 83.950 MHz
Logic Utilization	Used	Available	Utilization	Used	Available	Utilization
Number of Slice Registers	19529	64000	30%	2624	64000	4%
Number of Slice LUTs	20912	64000	32%	3753	64000	5%
Number of fully used LUT-FF pairs	937	39504	2%	398	5979	6%
Number of bonded IOBs	178	680	26%	178	680	26%
Number of Block RAM/FIFO	6	228	2%	37	228	16%
Number of BUFG/BUFGCTRLs	1	32	3%	1	32	3%
Number of DSP48Es	8	256	3%	8	256	3%

[mcgett]

The only item that is different in your tables is the "Number of fully used LUT-FF pairs". 

This line in the device utilization report is sub item in the "Number of LUT Flip Flop pairs used:" section which is intended to provide statistics for the design design.  The 39504 and 5979 represent the number of pairs that are in your design and has no relationship to the maximum number of possible LUT+FF pairs  in the device. 

[bwade]

You appear to be asking why the BRAM utilization is different for two synthesis runs. That question might be better asked on the synthesis forum.

[gszakacs]

The big difference seems to be Slice Register vs. Block RAM.  It seems that you

have some memory-like structures in your code that fit neatly into block RAM

in one case, and not in the other.  A likely cause for inferring lots of registers

instead of memory is the use of a reset term (real memories can be initialized

during config, but not "reset" to any value all at once).  Very often when this

happens you will get "info" messages telling you that XST has inferred a

very large number of slice registers and perhaps you could use RAM if you

didn't have a reset term.

Have you looked at the difference between the two codes to see if you

are doing something different in your memory descriptions between

the two?

-- Gabor

[rosalba_zarate]

Hello mcgett,

Yes, the only section that changes in availability is the "Numer of fully used LUT-FF pairs". Is it Ok if changes de availability? I thought availability was always the same for any design with the same number of LUT-FFs availables for all desgins.

Yes, the "Number of fully used LUT-FF pairs" is part of "Number of LUT Flip Flop pairs used".  When you say that provide statistics you mean is it ok if LUT-FFs change in different design because the fpga only took another arrengement? So LUT-FF are dynamic in their availability depending on the design?

For implementation of first design:

Number of LUT Flip Flop pairs used	24,252
Number with an unused Flip Flop	4,723	24,252	19%
Number with an unused LUT	12,539	24,252	51%
Number of fully used LUT-FF pairs	6,990	24,252	28%
Number of unique control sets	625
Number of slice register sites lost         to control set restrictions	75	64,000	1%

For implementation of second design:

Number of LUT Flip Flop pairs used	3,995
Number with an unused Flip Flop	1,371	3,995	34%
Number with an unused LUT	1,778	3,995	44%
Number of fully used LUT-FF pairs	846	3,995	21%
Number of unique control sets	86
Number of slice register sites lost         to control set restrictions	40	64,000	1%

[rosalba_zarate]

Hello gszakacs,

The big difference of first design with second desing was that I was using an addres generator unit with many registers, but in second desing I replace registers with BRAMs, so the FPGA could optimize design in space. 

My big problem was that I am worried about comparing two designs. But as you see the availability of the "Number of fully used LUT-FF pairs" is different, so I thought it could be a problem. I was expecting to have the same availability of LUT-FFs in both designs. But maybe there is not anything wrong, it is just that fpga arrenged everything in a different way. 

So, my big question is: There is always the same available number for "Number of fully used LUT-FF pairs" for any design?

[mcgett]

> Yes, the only section that changes in availability is the "Numer of fully used LUT-FF pairs".

> Is it Ok if changes de availability?

As I said earlier the LUT-FF pair number has nothing to do with the resources that are in the device.  It is a just a number based on your design for statistics.  If you had a design that was just an input buffer connected to an output buffer the number would be zero.

[rosalba_zarate]

---

mcgett wrote:

> Yes, the only section that changes in availability is the "Numer of fully used LUT-FF pairs".

> Is it Ok if changes de availability?

As I said earlier the LUT-FF pair number has nothing to do with the resources that are in the device.  It is a just a number based on your design for statistics.  If you had a design that was just an input buffer connected to an output buffer the number would be zero.

---

Ok, I understand.

From follow table (synthesize) can be seen that my first desing is using a total of 39,504 LUT-FF  from which are fully used 937. Second design  is using a total of 5979 LUT-FF from which 398 are fully used.  So, my first design is using much more LUT-FF than second one.

Device Utilization (HW)	1st Design Freq. 83.425MHz			2nd Design Freq. 83.950 MHz
Logic Utilization	Used	Available	Utilization	Used	Available	Utilization
Number of fully used LUT-FF pairs	937	39504	2%	398	5979	6%

Now, why in the implementation the "number of fully used LUT-FF" does it change with respect to the tables provided by SYNTHESIZE-XST?

1st design:

Number of fully used LUT-FF pairs

6,990

24,252

28%

2nd design:

Number of fully used LUT-FF pairs

846

3,995

21%

[mcgett]

> Ok, I understand.

> ...

> Now, why in the implementation the "number of fully used LUT-FF does it change"?

It appears that you do not understand.  Your design changed significantly so this number changed significantly.

[rosalba_zarate]

I understand the difference in registers because my design changed.

But my new question is a bit different. Let´s take the case of my first design.

For syntesize:

Device Utilization (HW)	1st Design Freq. 83.425MHz
Logic Utilization	Used	Available	Utilization
Number of fully used LUT-FF pairs	937	39504	2%

For implementation:

Number of fully used LUT-FF pairs

6,990

24,252

28%

Whit the same design I have different number of "Number of LUT Flip Flop pairs used". I obtain 39,504 when I synthesize and then 24,252 when I implement the same 1st design. I wanted to know the reason. Searching  and asking to my partners, they think (but not sure) that when you synthesize you only have an estimation of the resources of your desgin and sometimes it is optimized for speed, but when you implement is done a translation, mapping, and placing & routing. So, when design is implemented is arrenged in a different way deppending on the Syntehsis-XST(right click)/Process Properties/HDL Options. That is why they think the difference in the total "Number of LUT Flip Flop pairs used" of 39,504 and 24,252 . Maybe fpga optimeze everything in same design.

So, I am now asking about the difference in results in the one same design depending on synthesize or implementation. 

If I am wrong in something it would be helpful further information, links of anything about why the difference in the same design. Thank you in advance.