Synthesis

[diabolique0007]

I get the following error when i synthesize my code:

ERROR:Xst:785 line 26: Type must be constrained for this object : 'sys_memory1'.

INTERNAL_ERROR:Xst:cmain.c:3483:1.56.16.1 -  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Line 26 is a signal declaration:

signal sys_memory1,sys_memory2:array_type3;

And array_type3 is declared as:

type array_type3 is array(integer range 0 to 2147483647) of std_logic_vector(7 downto 0);

I don't understand why the error says type must be constrained when it is already constrained?

Thanks

[rcingham]

The error message may be misleading...

You appear to be inferring 2 * 2G * 8 bits = 32Gbits of memory.
What device are you targetting?
How much memory does it have?

[diabolique0007]

I'm trying to implement a system memory of 4 GB.

[rcingham]

"I'm trying to implement a system memory of 4 GB."

In an FPGA?

[diabolique0007]

I'm not sure about that as I won't be doing that but still I have to be sure that my design is synthesizable.

[mcgett]

> I'm not sure about that as I won't be doing that but still I have to be sure that my design is synthesizable.

There is no way to be able to synthesize/implement a 4 GB memory inside of any FPGA.  You need new code.

[eteam00]

There is no way to be able to synthesize/implement a 4 GB memory inside of any FPGA.  You need new code.

Or wait about 7 years for Virtex-10, perhaps?

-- Bob Elkind