Synthesis

[zorax85]

Using the following code lines, generates error (HDLParsers:808 - + can not have such operands in this context.).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Prom_BPI_IF_FSM is
    Port ( RESET: in  STD_LOGIC;
			  PROM_CE : out  STD_LOGIC;
           PROM_WE : out  STD_LOGIC;
			  PROM_OE : out  STD_LOGIC;
           PROM_ADV : out  STD_LOGIC;
           PROM_WAIT : in  STD_LOGIC;
           PROM_DATA : inout  STD_LOGIC_VECTOR (15 downto 0);
           PROM_ADDR : out  STD_LOGIC_VECTOR (27 downto 0));
end Prom_BPI_IF_FSM;



architecture Behavioral of Prom_BPI_IF_FSM is

type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, DATA_READING_PLUS, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count: std_logic_vector(27 downto 0);


begin

	prom_bpi_if_p: process(current_prom_bpi_state)

	begin

		next_prom_bpi_state <= current_prom_bpi_state;

		case current_prom_bpi_state is
			when IDLE =>
				if (RESET = '0') then
				next_prom_bpi_state <= START_READ;
				end if;
			
			when START_READ =>
				count <= "0000000000000000000000000000";
				PROM_CE <= '0';
				PROM_ADV <= '0';
				PROM_OE <= '1';
				PROM_ADDR <= (others => '0');
				next_prom_bpi_state <= DATA_READING;
				
			when DATA_READING =>
				if  count < ("0000000000000000000000001111") then
				PROM_CE <= '0';
				PROM_ADV <= '0';
				PROM_OE <= '0';
				PROM_ADDR <= (count);
				next_prom_bpi_state <= DATA_READING_PLUS; else
				next_prom_bpi_state <= FINISH; 
				end if;
				
			when DATA_READING_PLUS =>
				count <= count + "0000000000000000000000000001";
				next_prom_bpi_state <= DATA_READING;
			
			when FINISH =>
				PROM_CE <= '1';
				PROM_ADV <= '1';
				PROM_OE <= '1';
				next_prom_bpi_state <= IDLE; 
		end case;
	end process;
end Behavioral;

I would like just addressing a Parallel Prom through a CPLD. Can someone help me?

Thanks!

[rcingham]

You would have got an error at the same line if you had tried to simulate it, too.

[zorax85]

Yes, I know... that is why i'm asking for a solution...

[rcingham]

Try this...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Prom_BPI_IF_FSM is
    Port (RESET: in  STD_LOGIC;
	  PROM_CE : out  STD_LOGIC;
          PROM_WE : out  STD_LOGIC;
	  PROM_OE : out  STD_LOGIC;
          PROM_ADV : out  STD_LOGIC;
          PROM_WAIT : in  STD_LOGIC;
          PROM_DATA : inout  STD_LOGIC_VECTOR (15 downto 0);
          PROM_ADDR : out  STD_LOGIC_VECTOR (27 downto 0));
end entity Prom_BPI_IF_FSM;



architecture rtl of Prom_BPI_IF_FSM is

type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, DATA_READING_PLUS, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count: unsigned(27 downto 0);


begin

	prom_bpi_if_p: process(current_prom_bpi_state)
	begin
		next_prom_bpi_state <= current_prom_bpi_state;
		case current_prom_bpi_state is
			when IDLE =>
				if (RESET = '0') then
				next_prom_bpi_state <= START_READ;
				end if;
			when START_READ =>
				count <= (others => '0');
				PROM_CE <= '0';
				PROM_ADV <= '0';
				PROM_OE <= '1';
				PROM_ADDR <= (others => '0');
				next_prom_bpi_state <= DATA_READING;
			when DATA_READING =>
				if (count < 15) then
					PROM_CE <= '0';
					PROM_ADV <= '0';
					PROM_OE <= '0';
					PROM_ADDR <= STD_LOGIC_VECTOR(count);
					next_prom_bpi_state <= DATA_READING_PLUS; 
				else
					next_prom_bpi_state <= FINISH; 
				end if;
			when DATA_READING_PLUS =>
				count <= count + 1;
				next_prom_bpi_state <= DATA_READING;
			when FINISH =>
				PROM_CE <= '1';
				PROM_ADV <= '1';
				PROM_OE <= '1';
				next_prom_bpi_state <= IDLE; 
		end case;
	end process prom_bpi_if_p;

end architecture rtl;

[zorax85]

Thank you, now the syntax check is ok... I will prepare a testbench file for test the features.

[shyam4908]

Even your code work's but u need to un-comment "Numeric" package. But how ever the coding style is not code the best is as suggested "count + 1"

[zorax85]

I was changing something, but still I have problem. I don't understand why this FSM don't cycle on the DATA_READING state.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Prom_BPI_IF_FSM is
    Port ( 
	PROM_RESET               : in std_logic;
	PROM_CLK               : in std_logic;
	PROM_WAIT              : out std_logic;
	PROM_CE                : out std_logic;
	PROM_ADV               : out std_logic;
	PROM_OE                : out std_logic;
	PROM_WE                : out std_logic;
	PROM_ADDR              : out std_logic_vector(27 downto 0)
	--PROM_DATA              : in std_logic_vector(15 downto 0) -- remember to make inout
	);
end Prom_BPI_IF_FSM;



architecture rtl of Prom_BPI_IF_FSM is

type Prom_BPI_STATE is (IDLE, START_READ, DATA_READING, FINISH);
signal current_prom_bpi_state: Prom_BPI_STATE := IDLE;
signal next_prom_bpi_state: Prom_BPI_STATE;
signal count: unsigned(27 downto 0);
signal end_count: std_logic;
begin
end_count <= '1' when count= "0000000000000000000000000101010" else '0';

	prom_bpi_if_c: process(current_prom_bpi_state, PROM_RESET)

	begin
		
		count <= (others => '0');
		PROM_WAIT   <= '0';
		PROM_CE     <= '0';
		PROM_ADV    <= '0';
		PROM_OE     <= '0';
		PROM_WE     <= '0';
		PROM_ADDR   <= (others => '0');
		
		

		case current_prom_bpi_state is
			when IDLE =>
				if (PROM_RESET = '0') then
				next_prom_bpi_state <= START_READ;	else next_prom_bpi_state <= IDLE;
				end if;
			
			when START_READ =>
				count <= (others => '0');
				PROM_WAIT   <= '0';
				PROM_CE     <= '0';
				PROM_ADV    <= '0';
				PROM_OE     <= '1';
				PROM_WE     <= '0';
				PROM_ADDR   <= (others => '0');
				next_prom_bpi_state <= DATA_READING;
				
			when DATA_READING =>
				if  (end_count = '0') then				
				PROM_WAIT   <= '1';
				PROM_CE     <= '1';
				PROM_ADV    <= '1';
				PROM_OE     <= '1';
				PROM_WE     <= '1';
				count <= count + 1;
				PROM_ADDR <= STD_LOGIC_VECTOR(count);
				next_prom_bpi_state <= DATA_READING; else next_prom_bpi_state <= FINISH; 
				end if;

				
						
			when FINISH =>
				PROM_WAIT   <= '0';
				PROM_CE     <= '1';
				PROM_ADV    <= '0';
				PROM_OE     <= '1';
				PROM_WE     <= '0';
				PROM_ADDR   <= (others => '0');
				next_prom_bpi_state <= IDLE; 
		end case;
	end process prom_bpi_if_c;
	
	prom_bpi_if_r: process (PROM_CLK)
		
		begin
			if rising_edge(PROM_CLK) then
				
				current_prom_bpi_state <= next_prom_bpi_state; 
			end if;
	end process prom_bpi_if_r;
	
	
end architecture rtl;
				
				

[tetik]

First, the combinatorial process response only to PROM_RESET and current_prom_bpi_state.  You should add end_count to the sensitivity list.

Secondly, your PROM_ADD and count signals should be synchronous with the PROM_CLK.  Take them out from the combinatorial process and add then to a synchronous process.

Your code should look like this

if rising_edge(PROM_CLK) then

if state = DATA_READING then

  PROM_ADD <= std_logic_vector(count);

  count <= count + 1;

else

  count <= (others=> '0');

end if;

end if;

Good luck