Synthesis

[digimax]

 reg [87:0]Partial1; 

reg [21:0]Partial2; 

reg [127:0]X; 

reg [127:0]Y;

integer i;

always@*

begin

X[87:0]<=Partial1;

for(i=0;i<=21;i=i+1)

begin

Y[4*i]<=Partial2[i];

Y[(4*i+3):(4*i+1)]<=3'b0;

end

Y[127:88]<=0;

end

Errors:

ERROR:HDLCompilers:109 - "Top_Level_Put_Together.v" line 69 Most significant bit operand in part-select of vector reg 'Y' is illegal

ERROR:HDLCompilers:110 - "Top_Level_Put_Together.v" line 69 Least significant bit operand in part-select of vector reg 'Y' is illegal

ERROR:HDLCompilers:106 - "Top_Level_Put_Together.v" line 69 Illegal left hand side of nonblocking assignment

[digimax]

help!!!

[shantesh]

I'm not familiar with Verilog syntax but did you try Y[127:88] <= 40'b0;
You're assigning a single bit value to a vector !

[markcurry · Accepted solution]

Digimax,

Well first of all, you don't want to use non-blocking assignments here.  Change them to

blocking assignments.

Second (Decipering the forums messing up your posting) what you're trying to do in this line:

Y[ (4*i+3) : ( 4*i+1)] = 3'b0;

Isn't legal verilog.  Although you can see that this range is always 3 bits, this

wasn't readily apparant in the original Verilog-XL tools, thus was made illegal.

So, in verilog-2k, you've got new range operators to make these types of things work:

Y[  (4*i+3) -: 3 ] = 3'b0;

  or

Y[  (4*i+1) +: 3 ] = 3'b0;

The key to making this work is that the left side range operator can be variable.

The right side operator - the width - must be constant.

Give this a try, and you should be good to go.

[digimax]

your comments are quite helpful, thank you!