07-19-2011 03:11 PM
ERROR:HDLCompilers:109 - "Top_Level_Put_Together.v" line 69 Most significant bit operand in part-select of vector reg 'Y' is illegal
ERROR:HDLCompilers:110 - "Top_Level_Put_Together.v" line 69 Least significant bit operand in part-select of vector reg 'Y' is illegal
ERROR:HDLCompilers:106 - "Top_Level_Put_Together.v" line 69 Illegal left hand side of nonblocking assignment
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08-03-2011 10:39 AM
Well first of all, you don't want to use non-blocking assignments here. Change them to
Second (Decipering the forums messing up your posting) what you're trying to do in this line:
Y[ (4*i+3) : ( 4*i+1)] = 3'b0;
Isn't legal verilog. Although you can see that this range is always 3 bits, this
wasn't readily apparant in the original Verilog-XL tools, thus was made illegal.
So, in verilog-2k, you've got new range operators to make these types of things work:
Y[ (4*i+3) -: 3 ] = 3'b0;
Y[ (4*i+1) +: 3 ] = 3'b0;
The key to making this work is that the left side range operator can be variable.
The right side operator - the width - must be constant.
Give this a try, and you should be good to go.