Fatal error concerning bit array access

flatmush · ‎03-06-2009

I'm getting the following error when I try to synthesize the code below using XST:
FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

If I comment out the lines where the pDither arrays are accessed, then it compiles fine but that's probably due to the fact that it optimizes out the rams that I'm assuming it's having trouble infering. I changed the XST settings to do with infering rams but that didn't solve the issue, so now I'm completely lost.

I'm relatively new to verilog having been converted to it due solely to the fact that the schematic editor is so unbelievably buggy only to find that the verilog synthesis tools are equally buggy.
It seems that I spend more time fighting with the xilinx tools than actually working.

module vga_dither_spatial(iClk, iRed, iGreen, iBlue, iDither, iHSync, iVSync, oRed, oGreen, oBlue, oHSync, oVSync);

    input iClk;
    input [7:0] iRed;
    input [7:0] iGreen;
    input [7:0] iBlue;
    input [3:0] iDither;
    input iHSync;
    input iVSync;
    output [4:0] oRed;
    output [4:0] oGreen;
    output [3:0] oBlue;
    output oHSync;
    output oVSync;

    reg [4:0] oRed;
    reg [4:0] oGreen;
    reg [3:0] oBlue;
    reg oHSync;
    reg oVSync;

    reg pDitherRed[63:0];
    reg pDitherGreen[63:0];
    reg pDitherBlue[255:0];

initial begin
    $readmemb("c:/verilog/vga_dither_spatial_red.bin", pDitherRed);
    $readmemb("c:/verilog/vga_dither_spatial_green.bin", pDitherGreen);
    $readmemb("c:/verilog/vga_dither_spatial_blue.bin", pDitherBlue);
end

always @ (posedge iClk) begin
    oRed   <= iRed[7:3] + pDitherRed[{iRed[2:0], iDither[2:0]}];
    oGreen <= iGreen[7:3] + pDitherGreen[{iGreen[2:0], iDither[2:0]}];
    oBlue <= iBlue[7:4] + pDitherBlue[{iBlue[3:0], iDither[3:0]}];

    oHSync <= iHSync;
    oVSync <= iVSync;
end

endmodule

flatmush · ‎03-06-2009

OK, I've fixed the problem, is it that hard to say "Error: XST doesn't support bit addressed memory".

So for anyone else who comes across this problem you simply have to make the memory more than 1 bit wide for it to compile.

joshua_ · ‎02-27-2009

I'm not entirely sure if this is what you meant in your solution post, so I'll mention it here to be clear. What you probably meant was reg [255:0] pDitherBlue;, not reg pDitherBlue[255:0];. The reason is that you're not inferring a memory proper, but what you actually want to infer is a 256-input multiplexer with a 256-bit register loaded on the input lines.

That said, I agree that it is quite silly that you got the error that you did, and probably XST should have been able to synthesize it... but in terms of style, you really wanted a mux there, not a memory.

flatmush · ‎03-06-2009

I get what you mean but since I only wanted to read one bit at a time, then having a port width wider than one bit seems wasteful on some level, I was hoping it would be done in distributed memory which is a 1 bit wide 16-bit deep memory.
It seems to me that it makes more sense to define the bus width as the width of the data accesses you perform rather than using a larger bus and putting a multiplexer on it which does the same thing but is a less abstract way of thinking about it.

manojvasanthram · ‎04-10-2009

hi , vasanth here ... i too faced the same fatal error .... i dono how to apply the solution that has worked for u .... here is my code .... kindly help me ...

thanks a lot ...

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    20:12:16 04/10/2009
// Design Name:
// Module Name:    source
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module cam (wl,bl,blo,sl,clk,rd,out,srch);

//Parameter Declaration
parameter wrd_len = 4;
parameter mem_siz = 16;

//Port Declaration
    input [wrd_len-1:0]wl,sl;
    input clk,rd;
    input [wrd_len-1:0]bl;
//    inout [mem_siz-1:0]ml;
    output [wrd_len-1:0]blo,out;
    output [31:0]srch;
    integer i;

//Data Type Declaration
    reg [wrd_len-1:0]blo,out;
    reg [31:0]srch;
//    reg [mem_siz-1:0]ml;

//Local Variable Declaration
    reg [wrd_len-1:0]mem[0:mem_siz-1];
    reg cont = 1;
    initial begin
        $printtimescale;
      end
//Code Starts here
    always @ (posedge clk) begin
        if(wl !== 4'bzzzz) begin
            if (rd == 0) begin //wirte
                i = wl;
                mem[i] = bl;

            end
            if (rd == 1) begin //read
                i = wl;
                blo = mem[i];


            end
        end
        else begin //search
            cont = 1;
            srch = 0;
            for (i = 0; i<mem_siz ; i = i + 1) begin
            if (cont) begin
                out = 4'bxxxx;
                srch = srch + 1;
                if (mem[i] == sl) begin

                    out = i;
                    cont = 0;
                end
                end
            end
        end
    end
endmodule

flatmush · ‎03-06-2009

Whatever error you have is not the same as the error I got here, as far as I can tell, if you read the topic you should know that since your memory accesses are word sized and not single bits.
Also it's hard to debug code that's is so heavily abbreviated without comments, so the likelyhood of anyone correcting the error for you is very low.
If I were doing content addressable memory then I'd make a single memory cell and comparator, then hierarchically instantiate it.

manojvasanthram · ‎04-10-2009

hi, got the error rectified ..... the prblem was in the statement if( wl !== 4b'zzzz) .... i removed it and it worked fine .... but dono how is it actually caused an error ....