Synthesis

[david107]

I have this code in my description.....

proc0 : process(c5_load,c6_shift) is
variable buff :STD_LOGIC_VECTOR (7 downto 0):="00000000" ;
begin


if (c5_load = '1' and c5_load'event) then
buff:= ADDER_EXIT;
OUTPUT_A<=buff;	


elsif (c6_shift ='1' and c6_shift'event) then
A0 <= buff(0);
buff := buff(7) & buff(7 downto 1);
OUTPUT_A<=buff;	

end if;
	
end process proc0;

 but there is an error:

Signal buff cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

WHY?

Thanks so much

[eteam00]

Aside from the use of two different clocks for a single register -- c5_load and c6_shift -- not much to worry about.  Which FPGA family has more than one clock per register?

The use of blocking and non-blocking assignments in a clocked process is a bit sloppy.

You should ask your VHDL course instructor to give you a helping hand.

-- Bob Elkind

[bassman59]

---

david107 wrote:

I have this code in my description.....

proc0 : process(c5_load,c6_shift) is
variable buff :STD_LOGIC_VECTOR (7 downto 0):="00000000" ;
begin


if (c5_load = '1' and c5_load'event) then
buff:= ADDER_EXIT;
OUTPUT_A<=buff;	


elsif (c6_shift ='1' and c6_shift'event) then
A0 <= buff(0);
buff := buff(7) & buff(7 downto 1);
OUTPUT_A<=buff;	

end if;
	
end process proc0;

 but there is an error:

Signal buff cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

WHY?

Thanks so much

---

Yup, that's a bad synchronous description!
You should read the XST user guide to see what the tool expects.

[david107]

c5_load,c6_shift are two signals in input that come from my control unit.....

[eteam00]

c5_load,c6_shift are two signals in input that come from my control unit...

Does your control unit have a clock?

If so, will your control unit mind sharing its clock with the rest of your design?

Have you figured out the answer to this question: Which FPGA family has more than one clock per register?

Do you understand why I ask this question?

-- Bob Elkind

[harikr]

All the above comments are very valid.

If c5_load & c6_shift are two separate clocks in to this module it would be preferrable to split the single big process into two processes and if your code allows replace variable to signal declaration on the buff.

-Hari