01-05-2010 01:43 PM - edited 01-06-2010 12:26 AM
I want to add ready synthesized nmc files(modules) to my project. I know input and output numbers of that nmc files but I do not know these port names for this beforehand synthesized nmc files. So my question is:
How can I define this nmc files to my top module as a component. Do I have learn port names used during simulation or my I use some random names for ports and define that module as a module in my project. To specify the problem again: I know the exact input and output number of a ngc file but I dont know names of ports that are used during synthesis. So how can I use this ngc file as a module in my project.
I hope somebody can help, thanks in advance,
Solved! Go to Solution.
01-07-2010 10:26 AM
You can use NetGen to generate a simulation model in VHDL or Verilog for the ngc file. The VHDL/Verilg file should have all the ports for the ngc.
Take a look at the NetGen chapter in the Command Line Tools User Guide (http://www.xilinx.com/support/documentation/sw_ma