Synthesis

[collins_]

Few days ago, after update ISE 11.3 to 13.1... I noticed  that you can choose "VHDL-200X" in the vhdl source analysis standard of your project. It means we can use the new standard IEEE ( validated in 2008) ???? Not at all :(

**So we can forget unconstrained arrays/record :

    type std_logic_matrix is array (natural range <>) of std_logic_vector;
    signal M : std_logic_matrix(3 downto 0)(7 downto 0);

**So we can forget the simplified conditionnal expressions with ?=, ?/= ...

** So we can forget signal expressions in port map !

Most of updates in the new standard VHDL-200X (i'm not talking about the new libraries!) doesn't mean really and update of VHDL synthesis, the langage becomes just less prehistoric and more easy to use.

=>So my question is : when could we expect a true update of the VHDL standard for ISE ?

A second question comes :

why have I to use so old-fashion libraries in my design ?

Only the 1992's libraries STD_LOGIC_1164 and STD_LOGIC_SIGNED offer the opportunity to play with std_(u)logic_vector ( cause type (un)signed deosn't work very well with ISIM)

Thanks,

[rcingham]

Some of us professionals use ieee.numeric_std, and never std_logic_arith, std_logic_signed, etc.

[collins_]

Of course i would like to use numeric_bit to use shift, logical, comparaison and arithmetic functions with type signed and unsigned.And i know this library is more recent (1995! i'm crying now )

But most of Xilinx IP require type std_logic_vector and the 3 post-implementation simulations of ISIM doesn't work with types signed and unsigned.

So, i'm locked by std_logic_vector type!

Consequently i use:

ieee.std_logic_1164 for logical fonctions on type std_logic_vector (and rising/falling_edge() fonction)

ieee.std_logic_signed for comparaison and arithmetic functions on type std_logic_vector

ieee.std_logic_arith (uncompatible with numeric_bit!) only for the fonction conv_std_logic_vector that converts integer in std_logic_vector (when you're too lazy to write bits or hex :D )

Of course i would like to run after signed and unsigned types, but it's not the way of ISE until now: it works but not very well especially in simumation... I can survive with those 3 libraries and create everyday most of missing functions by hand. It's just boring and a waste of time... To avoid that, sometimes, i use the VHDL-200X libraries (VHDL-93 compatible) that you can find here : http://www.eda-stds.org/fphdl/

One topic talking about this "fight" between libraries (see the last comment) : http://www.velocityreviews.com/forums/t22337-std_logic_arith-numeric_std.html

[collins_]

I never use this kind of FPGA but their software looks like more up to date : quartus

Maybe Xilinx could start to lost some clients ?

[tembridis.com]

I might end up on a black list here by saying this, but I've been working with Quartus before and the ISE tool chain doesn't compare.

[collins_]

The topic here is to push Xilinx to update the standard of vhdl in ise, not to change to another competitor.

[tembridis.com]

Sorry, I did not want to imply to switch, that's a matter everyone has to decide for themselfs. I just wanted to point out that ISE is barely comparable to Quartus. Of course it would be very nice, if ISE would majorly improve to that same level of quality, but I wouldn't bet my wage on that. Not after seeing what happend with ISE 12.1 through 12.4.

[bassman59]

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collins_ wrote:

why have I to use so old-fashion libraries in my design ?

Only the 1992's libraries STD_LOGIC_1164 and STD_LOGIC_SIGNED offer the opportunity to play with std_(u)logic_vector ( cause type (un)signed deosn't work very well with ISIM)

 

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std_logic_arith/std_logic_signed were deprecated decades ago and were replaced with the superior numeric_std.

[bassman59]

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collins_ wrote:

Of course i would like to use numeric_bit to use shift, logical, comparaison and arithmetic functions with type signed and unsigned.And i know this library is more recent (1995! i'm crying now )

But most of Xilinx IP require type std_logic_vector and the 3 post-implementation simulations of ISIM doesn't work with types signed and unsigned.

So, i'm locked by std_logic_vector type!

Consequently i use:

ieee.std_logic_1164 for logical fonctions on type std_logic_vector (and rising/falling_edge() fonction)

ieee.std_logic_signed for comparaison and arithmetic functions on type std_logic_vector

ieee.std_logic_arith (uncompatible with numeric_bit!) only for the fonction conv_std_logic_vector that converts integer in std_logic_vector (when you're too lazy to write bits or hex :D )

---

You are not "locked" by std_logic_vector type.

There are simple conversion functions in numeric_std which allow for easy conversion between integer, natural, unsigned, signed and std_logic_vector.These functions have been available in the Xilinx tools for, oh, as long as I can remember.

There is absolutely no reason to use std_logic_arith.

[collins_]

Of course i can use signed or unsigned types. But, maybe is my mistake, i use a lot of Xilinx IPs. In most of my projects, I have to chain  more than 10 Xilinx IPs (multi-correlators) and like you know Xilinx IPs require std_logic_vector types! So I can't spend my time to convert. About ieee.std_logic_arith, I use it just for the fonction "conv_std_logic_vector" to convert integer in std_logic_vector that's all.

ISIM, the free simulation software included in ISE refuse (un)signed types in post-implementation and i have to simulate high-speeds parts of my design to see timing on internal signals (keep_hierarchy)...

I've heard that Symplify software offers opportunity to play with standard VHDL-200X ? Maybe is an expensive solution for me :(

Thanks for your comments.