Synthesis

[melika]

hello,

it's me again :|

I have this Info message for clock signal

INFO Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

I have added this "attribute" to my code:

attribute clock_signal : string;
attribute clock_signal of rd_thrd_latch_clk : signal is "yes";
attribute clock_signal of and127 : signal is "yes";
attribute clock_signal of round10 : signal is "yes";

and now I have this Info message again, but now no signal is marked.

What is the problem?

Thanks a lot.

[rcingham]

"What is the problem?"

That you are using signals generated by combinational logic as clocks. This indicates bad coding style, pehaps inferring latches. Post your code if you wish it to be critiqued.

[melika]

my code is structural based, this is part of my code that contains above signals.

rd_and_cntrl : entity work.and_std_logic(str)
port map( i => rd_sec_latch_out , j => and127 , q => rd_thrd_latch_clk);
-------------------------------------------------------------------------------------
rd_third_latch_cntrl : entity work. dff_inout_stdlogic(str)
port map( clk => rd_thrd_latch_clk, d => not_zero, q => rd_en); 

---------------------------------------------------------------------------------------

sixbit_cnt_control : entity work. dff_inout_stdlogic(str)
port map( clk => and127, d => not_zero, q => latch_out);  

-------------------------------------------------------------------------------------- 

cntrl_register : entity work.register(arch)
port map( clk => round10, d_in => after_sbox, d_out => enc_after_ff);

--------------------------------------------------------------------------------------

thanks for your guidance.

[bassman59]

---

melika wrote:

my code is structural based, this is part of my code that contains above signals.

rd_and_cntrl : entity work.and_std_logic(str)
port map( i => rd_sec_latch_out , j => and127 , q => rd_thrd_latch_clk);
-------------------------------------------------------------------------------------
rd_third_latch_cntrl : entity work. dff_inout_stdlogic(str)
port map( clk => rd_thrd_latch_clk, d => not_zero, q => rd_en); 

---------------------------------------------------------------------------------------

sixbit_cnt_control : entity work. dff_inout_stdlogic(str)
port map( clk => and127, d => not_zero, q => latch_out);  

-------------------------------------------------------------------------------------- 

cntrl_register : entity work.register(arch)
port map( clk => round10, d_in => after_sbox, d_out => enc_after_ff);

--------------------------------------------------------------------------------------

thanks for your guidance.

---

Yikes, gated clocks, asking for trouble.

[hgleamon1]

I apologise if I am cross-contaminating threads but the thought has occurred that this issue may well be related to another thread regarding clocks (or not): here

If these two threads are indeed related, or even from the same design, I feel you may be able to kill 2 birds with 1 stone by correcting your gated clock issues.

As I wrote, sorry if I am barking up the wrong tree.

Regards,

Howard

[melika]

Hi hgleamon1,

Thanks for follow-up,

Really all of my warnings and Info messages are for one design, one big design,

and I have raised them in separate posts because I thought that they are separated.

Please guide me how I can kill 2 birds with 1 stone  :-)

Thank you very much

[melika]

bassman59, I dont know how I do I solve this "info", and does this ("info" message) matter?

Thanks

[hgleamon1]

As bassman has pointed out, you seem to be using gated clocks. This is not good design practice and I can't really think of a reason why you might want to do it.

If you want a signal to clocked but not at the clock frequency, you would better off using a clock enable to clock the required signal through the gates, rather than ANDing a signal with your clock (which I inferred from the and127 signal described above). Thereby, your (genuine) clock remains a clock, routed through device clock resources available and your design remains synchronous.

I don't know your design or what you are trying to achieve but, from what you have described on your threads, I get the feeling that you could eliminate both combinatorial loops and the problems with your clock signals by investigating this line of thinking more closely.

Regards,

Howard

[eteam00]

melika,

Do you know how clock enables work?

You might be interested in post #8 of this thread.

-- Bob Elkind

[melika]

If you want a signal to clocked but not at the clock frequency, you would better off using a clock enable to clock the required signal through the gates, rather than ANDing a signal with your clock

I do that and INfo Xst:2169 was destroyed.

also I have this attribute :

attribute clock_signal : string;
attribute clock_signal of rd_thrd_latch_clk : signal is "yes";

Thanks,

I thought that clock gatting can reduce power because by register with enable port, input clk signal clocked every time At the time that was not needed.

Thanks A lot.