Synthesis

[melika]

hello,

I have this "Info" for my dual_ram code,

INFO Xst:738 - HDL ADVISOR - 512 flip-flops were inferred for signal <memory>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.

is it important?

my device: Spartan3_ XC3S400-5fg320

my code is attached.

thanks

[eteam00]

I'm not a VHDL wizard, so take what follows with a grain of salt...

This first process (see below) seems to be a clocked process.

• A clocked process needs only the clock and any asynchronous set/reset signals in the sensitivity list.

• Clock enables (including the wr_en and nor_a0a1 signals) should be inside the if rising_edge conditional clause

• Why are you using the falling edge of master_clk rather than the rising edge?  Is this an attempt to avoid collisions with READ operations?

Your code:

write_proc : process(master_clk, nor_a0a1,wr_en) is
  begin
    if nor_a0a1 = '1' then
      if (wr_en = '1') then
        if falling_edge(master_clk) then    --rising_edge(master_clk)
          memory(to_integer(unsigned(new_count))) <= d_in;
          end if;
        end if;            
      end if;
  end process;

There is a template for VHDL coding of dual-port RAM.  HDL templates are raised by clicking on the light-bulb icon within the ISE Navigator shell.

It might be helpful if you described how you intend to use your RAM.  Your coding style is a bit... unusual, and I'm not sure this coding style is helping you to accomplish your purposes.  And, like many user posting in these forums, you seem to avoid useful comments in your code -- as if they are expensive or somehow harmful to your well-being.

-- Bob Elkind

[sushantm]

The hint is in meassage itself.

http://www.dilloneng.com/documents/howto/ram_inference maybe helpful.

[sushantm]

Also you can refer

http://www.fpgarelated.com/usenet/fpga/show/85400-1.php

http://www.fpgarelated.com/usenet/fpga/show/28817-1.php

[sushantm]

Same issue is discussed & solved here by experts

Pls refer.

http://forums.xilinx.com/t5/Synthesis/Can-t-synthesize-variable-index-in-RAM/td-p/121284

[melika]

thanks for your guidance "eteam00" and "sushantm"

I got my issue resolved.

thanks for your attention to my code eteam00, i have changed my code as you can see in my attached code.

I found two reasons for my "info" message.

at first, if  memory signal(in my code) should be used only the right side, this "info" message will appear plus the warning that said this signals is delcared but never used.

and, the second reason is for this line of my code "d_out <= memory(dec_counter(rd_value_int))"

with this line i have two "info" message, info738 and  info2261.

INFO Xst:2261 - The FF/Latch <value_int_0> in Unit <ram_xilinx_quest> is equivalent to the following FF/Latch, which will be removed : <test_new_count_0>.

dec_counter has constant value and by info2261 will be removed.

finally i have changed my code, as you can see in ram_xilinx_qust2.doc

now i have only one "info" :

INFO Xst - The small RAM <Mram_memory> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.

and i think it's not important, is it true?

[eteam00]

I got my issue resolved.

Good news!

now i have only one "info" :

INFO Xst - The small RAM <Mram_memory> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.

and i think it's not important, is it true?

If you have plenty of LUTs, then you should be happy.  If you "run low" on LUTs, you can switch to BRAMs whenever you feel the need.  You may want to try this option, just to prove to yourself that it can be done.

Thanks for the feedback.  If you finished with this particular problem, please mark the thread as "solved".

Good luck to you...

-- Bob Elkind

[melika]

If you have plenty of LUTs, then you should be happy.  If you "run low" on LUTs, you can switch to BRAMs whenever you feel the need.  You may want to try this option, just to prove to yourself that it can be done.

my device is XC3S400, please guide me. i don't know i have plenty of LUTs or not?

thanks a lot.

[eteam00 · Accepted solution]

my device is XC3S400, please guide me. i don't know i have plenty of LUTs or not?

That depends on how many LUTs you need for the rest of your design, yes?

Synthesise your design, and the Design Summary report in ISE will tell you how many LUTs are used and how many are yet unused.

Your RAM is 16x32b.  This requires 32 LUTs in the Spartan-3 devices.  The XC3S400 has 7,168 LUTs (two per slice, or 8 per CLB).

-- Bob Elkind

[melika]

OK, thanks.