04-11-2012 04:49 AM
I am developing a component which I want to use both for Spartan 3E and Spartan 6 FPGA families. This block contains instantiations to both primitives and IP-Core blocks generated for each of those families.
In case of the primitives used, I select the one to be synthesized with an if-generate construction. No problem.
The problem comes when I try to make something similar for a IP-Core block generated with the BRAM Generator v6.2. In the HDL functional model I can see that the devide is specified in the generic map of the component instantiation. Thus, I copied that HDL functional model in a new custom VHDL block of mine with that clause variable (a string I use through all the design to toggle between both devices)... but it does not work...
Does anybody know how to do this properly?
Thank you in advance.
Solved! Go to Solution.
04-11-2012 05:51 AM
the functional model is for simulation only.
It refers to the XilinxCorelib simulation library.
The models therein might need some information about the target family to choose the corect memory sizes etc..
You need to instantiate the correctly defined netlists for your target family which need to have different names.
for that you can create two cores (one for S3 and one for S6 and instantiate them with an if_generate according to some Generic that specifies the target family.
if TARGET_S3 generate
if TARGET_S6 generate
Here the generics are of Type boolean.
You can use assert statements to check that not both generics are set to true at the same time
assert (TARGET_S3 /= TARGET_S&) report "Enable only one Target Family Generic." severity failure;
Have a nice synthesis
04-11-2012 06:51 AM
Thank you very much for your answer. I will then do as you say.
Some of the BRAMs I will be using have to be initialized with some data (different each). How can I specify that each of them has to be initialized with the different data files (.mif or .coe) I have prepared? All that data can change between each time I will synthesize the whole design... I think it will be a similar problem to the one with the different devices, but I cannot create a new IP-Core with different .coe files each time as it will be a total waste of time and the people which will be generating and testing that data (it is some calibration data) have not FPGA knowledge.
Thank you again for your help :)
04-11-2012 11:17 PM
IP cores are normally intended to have a fixed function.
If there's no other way to change the initialisation data at synthesis time e.g. by some generic then there's always the data2mem tool that can change memory contents on the bitstream level.
Only thing that has to be provided is the correct name and path of the BRAM inside the design.
Some demo and a good explanation how to adapt paths and instance names might be all the customer needs.
If it's just for calibration data and the design is fixed at that time, data2mem would be the tool of choice anyway.
Have a nice synthesis
04-12-2012 11:28 PM
that's a good question for some Xilinx employee to answer.
I didn't know yet that data2mem is not capapble of handling all actual FPGA families alike.
Maybe you should open a new thread asking for a data2mem replacement for S6 devices, or directly contact someone at Xilinx. If you get a solution it would be good to post it here as well.
Have a nice synthesis
04-12-2012 11:35 PM
Thank you very much for your help... I will try to do so, but I cannot understand how there can be no method to initialize RAMs/ROMs in an automated way for actual devices...
I will see if I get some information about this issue of data2mem .
04-13-2012 02:37 AM
Unfortunately data2mem does not support Spartan6 devices
From the Data2Mem User Guide (UG658 v13.3), page 6:
Data2MEM supports the following devices:
• Spartan-3A DSP
What convinced you that Spartan-6 is not supported?
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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