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Regular Contributor
asicuser
Posts: 60
Registered: ‎03-02-2010
0

Illegal redeclaration of input 'in' as a reg

[ Edited ]

I 've got this (http://pastebin.com/p26QQ2cx):

 

module modname(clk, in, out,reset, ratio); parameter OUTPUT_WIDTH = 64; parameter INPUT_WIDTH = 6; input reset; input clk; input [INPUT_WIDTH-1:0] in; output [OUTPUT_WIDTH-1:0] out; output [8:0] ratio; reg [OUTPUT_WIDTH-1:0] out; reg [8:0] ratio; reg [INPUT_WIDTH-1:0] in;always@(posedge clk or negedge reset or in) if (~reset) begin out = 0; ratio = 0; end else begin numcrunch(out, ratio, in); end.....endmodule

 

 It gives an error on the line:

reg [INPUT_WIDTH-1:0] in;

 

Illegal redeclaration of input 'in' as a reg 

 

 

Message Edited by asicuser on 03-02-2010 09:13 AM
Contributor
head_up
Posts: 26
Registered: ‎10-11-2009
0

Re: Illegal redeclaration of input 'in' as a reg

This is your code (in readable form):

 

module modname(clk, in, out,reset, ratio);
     parameter OUTPUT_WIDTH = 64;
     parameter INPUT_WIDTH = 6;
     input     reset;
     input     clk;
     input    [INPUT_WIDTH-1:0]     in;
     output    [OUTPUT_WIDTH-1:0]     out;
     output  [8:0]  ratio;
     reg [OUTPUT_WIDTH-1:0] out;
     reg [8:0] ratio;
     reg [INPUT_WIDTH-1:0]     in;


     always@(posedge clk or negedge reset or in)
     if (~reset)
        begin   
        out = 0;
        ratio = 0;
        end   
    else
        begin
            numcrunch(out, ratio, in);
        end

    .....endmodule

 

The "error" is right - u define <in> (green color) as input - this is ok, but after this again as <reg> (red color). this is wrong, because the inputs cannot be redefined! The <inputs> are treat as <wire> (they cannot hold value).

Sorry for my bad english, but i hope u understand what i try to explain.

Regular Contributor
asicuser
Posts: 60
Registered: ‎03-02-2010
0

Re: Illegal redeclaration of input 'in' as a reg

Thank you for the response. My apologies for the bad format, I reposted it to pastebin.

 

I removed reg [INPUT_WIDTH-1:0] in; from the code. When I do a syntax check, it now gives:

Unexpected in event in always block sensitivity list for the line: always@(posedge clk or negedge reset or in)

 

I also tried   wire [INPUT_WIDTH-1:0] in; which also results in the same error.

Contributor
head_up
Posts: 26
Registered: ‎10-11-2009
0

Re: Illegal redeclaration of input 'in' as a reg

[ Edited ]

u dont understand me: u say

input    [INPUT_WIDTH-1:0]     in;

and this is all! <in> is defined as input with name <in>, and u must NOT redefine <in> as anything else (reg, wire ... and so on). now u can use <in> where u need, but <in> cannot hold value (just like <wire>).

 

always@(posedge clk or negedge reset or in)
    if (~reset)
        begin   
        out = 0;
        ratio = 0;
        end   
    else
        begin
                   numcrunch(out, ratio, in);
        end

 

--> (red color) is not good idea (may be u will have other warnings/errors about this). I dont know what do your design (and i will not read all source code), but may be u must read some book about Verilog (orVHDL if u like it), synthax and the rules for modeling synchronous/combinational logic. Something like "HDL Chip Design" (Douglas J Smith) or http://www.asic-world.com/verilog/veritut.html

http://www.doulos.com/knowhow/verilog_designers_guide/  or just use google! Go ahead :)

 

PP I hate "," in url....

Message Edited by head_up on 03-02-2010 11:16 AM