04-24-2012 08:57 AM
How can I include Blocks of VHDL code into a Verilog ISE project.
Maybe I can use a Verilog Wrapper that Wraps VHDL hierarchical Blocks into the design.
How would I write the wrapper if I can do this.
Solved! Go to Solution.
04-24-2012 11:29 AM
If you use the GUI, you can just add the VHDL entities to the project and select "view instantiation template"
to see how to instantiate it in Verilog. You shouldn't need a wrapper file.
Is this what you were looking for, or were you looking for a way to end up with a Verilog-only
project to avoid mixed-language? The latter would require you to first build the VHDL code
to create a .ngc file, and then use a Verilog black box (empty module with only port definitions)
that has the same ports and name as the .ngc file.