Synthesis

[bonsaipappel]

Hello,

I've a question about how XST is interpreting Verilog statements.

I have an FIFO with an 1537 bit wide output register and I need to grep 13-bit wide chunks (this are ADC values). This chunks are extended to 16-bit (Bits [15:13] = 3'b000) and sorted into a 16 bit wide BRAM.

Here is a Code snippet:

wire  [1536:0]  packet_fifo_dout;
reg   [9:0]       bram_adc_cnt_r;
reg   [15:0]     bram_dina_r;

...
"I do this inside of a FSM"
{
SOME_STATE: begin
  if (bram_adc_cnt_r < bram_adc_max_r) begin
    bram_dina_r     <= {3'b000, packet_fifo_dout[(bram_adc_cnt_r*13)+:13]};
    bram_adc_cnt_r <= bram_adc_cnt_r + 1;
  end
end
}

 After the Synthesis the XST log report the following:

Found 3061-bit shifter logical right for signal <n1887> created at line 500
...
inferred   1 Combinational logic shifter(s).

 The reported Line 500 is the one with the

bram_dina_r <= {3'b000, packet_fifo_dout[(bram_adc_cnt_r*13)+:13]};

 statement.

Also the synthesis of this module takes very log compared to the rest of the design.

I assume this is because of the 3061-bit shift register.

Is there any other Verilog statement which can be used to make this statement more synthesizable?

Best regards,

Volker

[eilert · Accepted solution]

Hi Volker,

your code example is a little short to say something specific.

What makes me wonder the most is the term "combinational shift register".

Does this mean there's no clock used?

While your intention seems to be quite clear. You want to take a number of 13 bit fields out of the extremely wide fifo_dout (why is it a wire and not a reg?) and put it into some BRAM.

Whatever XST creates out of your HDL description, the approach will in any way create some big combinatorical chunk of logic, slowing down your design. I would have expected something like a giant MUX with N 13-bit inputs.

My idea for coding this would be to create a true shift register from the fifo_dout signal, shifting 13bits at each rising clock edge. Then you can conect the bits of the first data word to the BRAM and after writiung them the next word appears there automatically. No logic required, just FFs and wires.

Of course you have to deal somehow with the fact that 1537 is not a common multiple of 13, but maybe you are just processing a smaller section of that signal.

Have you simulated your code?

Does the synthesis result (RTL-Schematic) make sense at all?

How aboout Fmax in the synthesis report(*.syr file)?

Have a nice synthesis

  Eilert

[bonsaipappel]

Hi Eilert,

thank you for your reply. I thought my HDL description would create a shift register but this was not the case. Thanks to your input I had another look to the code and changed the HDL to the following:

bram_dina_r[15:13]  <= 3'b000;
bram_dina_r[12:0]   <= adc13_shift_r[12:0];
adc13_shift_r          <= {13'd0, adc13_shift_r[1536:13]}; // shift by 13 bits every clock

 where "adc13_shift_r" is the registered output of the fifo_dout.

Now the "Inferred Combinational logic shifter" is gone and the synthesis time dropped by 50%.

Thanks again.

Best regards,

Volker