05-31-2012 10:05 PM
I am having problems with macros not being recognized. So I made this simple test:
`timescale 1ns / 1ps
`define VLAD 5
reg [7:0] test;
assign test= VLAD + 1;
When I Synthetize it I get this error:
ERROR:HDLCompilers:28 - "main.v" line 12 'VLAD' has not been declared
Any idea why? What I am doing wrong?
I tried both Verilog-200X and Verilog-93 to no avail. I am using the latest ISE available (14.1?)
Solved! Go to Solution.