Synthesis

[vladstamate]

Hi all,

I am having problems with macros not being recognized. So I made this simple test:

`timescale 1ns / 1ps

`define VLAD 5

module main(
);

reg [7:0] test;

initial
begin
assign test= VLAD + 1;
end

endmodule

When I Synthetize it I get this error:

ERROR:HDLCompilers:28 - "main.v" line 12 'VLAD' has not been declared

Any idea why? What I am doing wrong? 

I tried both Verilog-200X and Verilog-93 to no avail. I am using the latest ISE available (14.1?)

Regards,

Vlad.

[eilert · Accepted solution]

Hi Vlad,

shouldn't it belike this:

assign test= 'VLAD + 1;

                               ^

                               see the little tick there?

Have a nice synthesis

  Eilert

[vladstamate]

Ah!! Yes, thank you very much! That worked! I can now get back to my design.

Regards,

Vlad.