Synthesis

[nemanja_savic]

Hi all,

I am designing some simple system, and I need maximum clock frequency estimation.

There are two clock frequencies mentioned id syntesis report:

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 3.188ns (Maximum Frequency: 313.632MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 4.326ns
   Maximum combinational path delay: No path found

and :

Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 2.353ns (frequency: 425.026MHz)
  Total number of paths / destination ports: 6 / 3

Now I am in doubt what is maximum frequency of the overall system.

Thank you

[austin]

n,

Until you place and route the design with a period constraint, this from synthesis is just a guess.

[nemanja_savic]

Ok, thak you for your answer.

What is practical meaning of those information that i got from synthesis?

[austin]

n,

A rough estimate.