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## Synthesis

Visitor
Posts: 5
Registered: ‎01-10-2012

# Multiple signals in the sensitivity list.

I want to have multiple signals with negative edge triggering at the sensitivity list. But when i add more than

1 signal I get the error specified at the bottom. If I remove 'negedge', then i can have the 3 signals.

How can make this code work. I want to trigger the always block at negaive edges of all 3 signals.

Thank you.

-----------------------------------------------------------------------------------------------------------------------------------------------------

module switch(_1U,I1,_2D,_2U,I2,_3D,I3,L1,L2,L3,L4,reset);

input _1U;     //SW_0
input _2U;  //SW_1
input _2D;  //SW_2
input _3D;  //SW-3

input I1;   //Down
input I2;   //Enter
input I3;   //UP

input reset; //Left

output L1;
output L2;
output L3;
output L4;

reg count;
reg L1;
reg L2;
reg L3;
reg L4;

//     reg FL1;
//     reg FL2;
//     reg FL3;

wire T12;
wire T13;
wire T21;
wire T23;
wire T31;
wire T32;

wire temp;

assign     T12 = L1 & ( ~I2 | _2U | _2D);
assign        T13 = L1 & ( ~I3| _3D);
assign        T21 = L2 & (~I1 | _1U);
assign        T23 = L2 & (~I3 | _3D);
assign        T31 = L3 & (~I1 | _1U );
assign        T32 = L3 & (~I2 | _2D | _2U);

always @ ( negedge I2 or negedge I1 or negedge I3 )     <= Touble making sensitivity list
begin

if (~reset)
begin
L1 = 1'b1;
L2 = 1'b0;
L3 = 1'b0;
end
else
begin

L4 = 1'b1;
if (T12 == 1'b1)
begin
L1 = 1'b0;
L2 = 1'b1;
end
else if (T13 == 1'b1)
begin
L1 = 1'b0;
L3 = 1'b1;
end
else if (T21 == 1'b1)
begin
L2 = 1'b0;
L1 = 1'b1;
end
else if (T23 == 1'b1)
begin
L2 = 1'b0;
L3 = 1'b1;
end
else if (T31 == 1'b1)
begin
L3 = 1'b0;
L1 = 1'b1;
end
else if (T32 == 1'b1)
begin
L3 = 1'b0;
L2 = 1'b1;
end
end
end
endmodule

Here is the error i get

Analyzing top module <switch>.
ERROR:Xst:899 - "switch.v" line 88: The logic for <L1> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "switch.v" line 89: The logic for <L2> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "switch.v" line 94: The logic for <L3> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

Found 3 error(s). Aborting synthesis.

NOTE : It seems the problem is with the reg variables L1,L2,L3.
But i don't know how to handle it properly

Super Contributor
Posts: 142
Registered: ‎09-11-2007

# Re: Multiple signals in the sensitivity list.

The error is telling you that there is no flip-flop in your device that has three clock inputs.  Think of another way to code your logic.  Try drawing a schematic first, with normal flip-flops.

Barry

Expert Contributor
Posts: 7,505
Registered: ‎07-21-2009

# Re: Multiple signals in the sensitivity list.

[ Edited ]

You need to re-read the Verilog primer section which explains blocking and non-blocking assignments.

Generally speaking, using combinatorial logic for clocks is a bad idea in FPGA designs.  This is generally called 'asynchronous design', and is not supported by the Xilinx development tools.

You will be much better served if you learn the fundamentals of single-clock synchronous logic system design.  This is the basic approach used for most FPGA designs, and is the approach for which FPGA devices and toolsets have been optimised.  This is (most likely) what you will use in your future career as an FPGA designer.

Some more suggestions:

• Use meaningful variable names.  For example --

_1U, _2U, _2D, _3D, I1, I2, I3

vs.

Switch_0, Switch_1, Switch_2, Switch_3, Down, Enter, UP

• Learn to comment your code, as a matter of habit.  This will save you more time than you can possibly imagine, over the course of your design career.

-- Bob Elkind

SIGNATURE:

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Expert Contributor
Posts: 4,741
Registered: ‎02-25-2008

# Re: Multiple signals in the sensitivity list.

udaranga wrote:

I want to have multiple signals with negative edge triggering at the sensitivity list.

No, you don't.

----------------------------------------------------------------
Yes, I do this for a living.