Synthesis

[kirantherock]

Hi there!
I wrote two programs in VHDL, one to generate a PRBS sequence and another to generate a square signal of 100 Mhz. For both these signals I took the output at the SMA port on the FPGA board (Xilinx SP601). Now I want to multiply these two signals and get the output again at the SMA port.

For the PRBS sequence, I got the output in the register

data_out std_logic_vector (9 downto 0)

 To get the data serially out from the SMA port I created another register 'mlbs_out' which is an 'std_logic'. I copied the data into mlbs_out in the following manner:

mlbs_out <= data_out(9);
data_out(9 downto 1) <= data_out(8 downto 0);

For the square signal, I used the ODDR2 instantiation and simply got the output in a register 'bout' which is an 'std_logic'

ODDR2_inst : ODDR2
   generic map(
     DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => bout, -- 1-bit output data
      C0 => cout, -- 1-bit clock input
      C1 => cout_n, -- 1-bit clock input
      CE => '1',  -- 1-bit clock enable input
      D0 => '0',   -- 1-bit data input (associated with C0)
      D1 => '1',   -- 1-bit data input (associated with C1)
      R => '0',    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );

Now when I use the simple multiplication operator I get an error. The code I use is:

LED_OUT <= ((mlbs_out)*(bout));

The error I get is, "found '0' definitions of operator "*", cannot determine exact overloaded matching definition for "*" "
I am using "STD_LOGIC_UNSIGNED.ALL" library. I also tried using the "ARITHMETIC.ALL" library and then writing the sign of the signals everywhere but to no avail.
Could someone please explain how I can get over this problem?

[austin]

k,

You are not writing a program, you are building hardware.  Wires, gates, flip flops.  If you wish to multiply, you place the two parallel words into the DSP48 block, and get the product.

http://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf

and read:

http://forums.xilinx.com/t5/PLD-Blog/How-Shall-I-Start-Master/ba-p/209443

There is no parallel "square wave" here, so that makes no sense.

If you are mixing two signals, in a communications channel sense, the operator is exclusive OR of the carrier, with the information.  If the information is in serial form, you may exclusive OR that with another signal.  The clock of hte LSFR makes no sense to XOR with the output of the LSFR...unless that is what you really want to do.

[bassman59]

---

kirantherock wrote:

Hi there!
I wrote two programs in VHDL, one to generate a PRBS sequence and another to generate a square signal of 100 Mhz. For both these signals I took the output at the SMA port on the FPGA board (Xilinx SP601). Now I want to multiply these two signals and get the output again at the SMA port.

For the PRBS sequence, I got the output in the register

data_out std_logic_vector (9 downto 0)

 To get the data serially out from the SMA port I created another register 'mlbs_out' which is an 'std_logic'. I copied the data into mlbs_out in the following manner:

mlbs_out <= data_out(9);
data_out(9 downto 1) <= data_out(8 downto 0);

For the square signal, I used the ODDR2 instantiation and simply got the output in a register 'bout' which is an 'std_logic'

ODDR2_inst : ODDR2
   generic map(
     DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" 
      INIT => '0', -- Sets initial state of the Q output to '0' or '1'
      SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
   port map (
      Q => bout, -- 1-bit output data
      C0 => cout, -- 1-bit clock input
      C1 => cout_n, -- 1-bit clock input
      CE => '1',  -- 1-bit clock enable input
      D0 => '0',   -- 1-bit data input (associated with C0)
      D1 => '1',   -- 1-bit data input (associated with C1)
      R => '0',    -- 1-bit reset input
      S => '0'     -- 1-bit set input
   );

Now when I use the simple multiplication operator I get an error. The code I use is:

LED_OUT <= ((mlbs_out)*(bout));

The error I get is, "found '0' definitions of operator "*", cannot determine exact overloaded matching definition for "*" "
I am using "STD_LOGIC_UNSIGNED.ALL" library. I also tried using the "ARITHMETIC.ALL" library and then writing the sign of the signals everywhere but to no avail.
Could someone please explain how I can get over this problem?

---

You want to use the numeric_std library (std_logic_arith really needs to die in a fire, and Xilinx really needs to update their documentation).

But before that, the arguments to the multiplier have to be the same width. bout is simply a bit, and you need to multiply words. Think about it. If you multiply foo * 1, your result is foo. If you multiply foo * 0, your result is 0. That's not very interesting.

Also, I have no idea why you're even using the ODDR2, because an ODDR2 output is an FPGA pin. 

So what you're trying to do isn't at all clear.