Synthesis

[ianscott]

Please help!

I have a simple FSM below to monitor the state of some signals coming from a FIFO.  I also pass some signals through to outputs for debugging.  However, one of my GPIO lines (GPIO14) does not show up as an output pin in the RTL.  Can anybody tell me why it has apparently been trimmed away, despite there being no warnings or errors?  Code is below, synthesis report is attached.

Thanks in advance.

Ian

--------

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity XM_SIPO_FIFO is

port (
  
  IS_FULL   : in  STD_LOGIC;
  DATA_PRESENT : in STD_LOGIC;
  SYN     : in STD_LOGIC;

  -- Pass thru Flash control lines
  ASIC_FLASH_OE_N  : in STD_LOGIC;
  FLASH_OE_N: out STD_LOGIC;
  
  -- Reset lines
  MRESET :  in STD_LOGIC; -- power on reset, active low
  
  -- mirror my input out the GPIO 
  GPIO10 :  out STD_LOGIC;
  GPIO11 : out STD_LOGIC;
  GPIO14 :  out STD_LOGIC
   );

end XM_SIPO_FIFO;

architecture behavior of XM_SIPO_FIFO is
 
 signal RESET_IN  : STD_LOGIC;
 
 -- Simple 3 state state machine for stream sync with SYN signal
   type stream_state_type is (STATE_STREAM_WAITING_SYNC, STATE_STREAM_HAS_SYNC, STATE_STREAM_OVERFLOWED);
   signal StreamSyncState  : stream_state_type  := STATE_STREAM_WAITING_SYNC;

-----------------------------------------------------------------

 -- aliases to allow the flash control bus to be passed through.
 signal OE      : std_logic;
 signal SS_State_has_sync : std_logic;
 
-----------------------------------------------------------------

 begin

 GPIO10 <= MRESET;
 GPIO11 <= OE;
 GPIO14  <= SS_State_has_sync; --   <-- why does this output not show up as a pin in the RTL?

 RESET_IN  <= MRESET;
 OE <= ASIC_FLASH_OE_N;
 FLASH_OE_N <= OE;
 
 SS_State_has_sync <= '1' when StreamSyncState = STATE_STREAM_HAS_SYNC else '0';
 
 
----------------------------------------------------------
------ every time we fill up we need to re-sync at the next SYN positive edge
process (SYN, IS_FULL, DATA_PRESENT, RESET_IN, StreamSyncState)
begin
 
 if ( RESET_IN = '0' or (DATA_PRESENT = '0' AND StreamSyncState = STATE_STREAM_OVERFLOWED) ) then
  StreamSyncState <= STATE_STREAM_WAITING_SYNC;  -- RESET or we are empty following an overflow
 elsif IS_FULL = '1' then
  StreamSyncState <= STATE_STREAM_OVERFLOWED; 
 elsif ( rising_edge(SYN) AND StreamSyncState = STATE_STREAM_WAITING_SYNC ) then
  StreamSyncState <= STATE_STREAM_HAS_SYNC; -- only move to sync state from empty
 end if;
 

end process;

end behavior;
 

[bobster_the_lobster]

Hi Ianscott,,,, its being taken out because you told it to.

look at these parts of the description in your code.....

SS_State_has_sync <= '1' when StreamSyncState = STATE_STREAM_HAS_SYNC else '0'

StreamSyncState <= STATE_STREAM_HAS_SYNC;

GPIO14  <= SS_State_has_sync;

My advice is start again, draw a circuit, and describe the circuit.

Kind Regards Bobster

P.S. the structure is quite confusing to read.. have a look at the xst guide

[ywu]

I counted 9 IOs in your VHDL port list and the synthesis report shows 9 IOs. Why do you think GPIO14 is optimized out?

Cheers,

Jim

[ianscott]

Thanks for looking, Bobster.

I understand that the value will always be zero and was expecting to see GPIO14 always connected to ground in the RTL.  However in the RTL, GPIO14 is not shown as a pin and is not listed as a pin either.  It does show up in a bus combined with StreamSyncState, but it is never exposed from that bus.  That is the part that had me alarmed.

Any ideas why?

Ian

p.s.  Sorry about the confusing structure - I had some leftover bits of things I was trying in there, and it was also part of a larger project I had slimmed down for demonstration purposes.

[ianscott]

Jimwu-

Thanks for looking.

I had also counted nine IOs but when it came to listing the pins when viewing the RTL, GPIO14 was missing as a pin.  I was expecting to see a grounded pin.  (When viewing the RTL schematic in ISE 9.2.04i, View by category only shows 8 pins and no GPIO14 port is shown on the schematic)

Any ideas?

Thanks!

Ian

[ywu]

That could well be a display bug in the ISE 9.2 RTL schematic viewer. What really matters is that GPIO14 shows up in the final implementation result.

FWIW, I tried your code in 11.2, GPIO shows up in the RTL schematic viewer (see attached screenshot).

Cheers,

Jim

Message Edited by jimwu on 09-11-2009 12:02 PM