Synthesis

[lakshmanan.ag]

Hello everyone,

I am a student and I am trying to build a model of olfactory lobe of brain for my project using FPGA. Firstly, I have to build a model of singular neuron and later connect these blocks in order to build the lobe. Inorder to build a neuron model I am asked to model the synapse(junction of connection between two neurons), soma(neuron body), axon(long tail of neuron) seperatley and later join them to obtain the neuron model. I wrote the following code (below)for modelling synapse. When I simulate it by suitable test bench, I get the expected beautiful sawtooth waveform using ModelSim (Figure 1 - shown in the attachment). 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity synapse_model_vhdl is

port(  syn_current : out std_logic_vector(31 downto 0);

syn_in      : in std_logic;

syn_weight  : in std_logic_vector(31 downto 0)

        );

end synapse_model_vhdl;

architecture Behavioral of synapse_model_vhdl is

signal adsub_in     : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal adsub_out    : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal acc_prev_out : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal acc_curr_out : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal shift_out    : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

constant tau        : integer                          := 11;

signal syn_clk      : std_logic;

signal shift_process: bit_vector(31 downto 0);

signal shift_temp   : bit_vector(31 downto 0);

begin

syn_clk <= syn_in;

synapse_calc: process is 

begin

if syn_clk = '0' then                                            

adsub_in <= "00000000000000000000000000000000";             

elsif syn_clk = '1' then                                       

adsub_in <= syn_weight;                                   

end if;                                                         

shift_process <= to_bitvector(acc_prev_out);    --  \\

shift_temp    <= shift_process sra tau;        -- Shifter code

shift_out     <= to_stdlogicvector(shift_temp); --  //

adsub_out <= adsub_in - shift_out;              -- Subtractor block

acc_curr_out <= acc_prev_out + adsub_out;       -- Accumulator block          

wait for 500 ps;                                -- For simulation only

acc_prev_out <= acc_curr_out;

wait for 500 ps;                                -- For simulation only

end process synapse_calc; 

syn_current <= acc_curr_out;

end Behavioral; 

The problem is:

I am experiencing difficulty while trying to synthesize-XST (viewing the RTL schematic, technology schematic of) the synapse model. 

Xilinx ISE shows compilation error while I have 'wait for 500 ps' during RTL schematic generation stages: 

ERROR:HDLParsers:1015 - "D:/Xilinx92i/synapse_model_final/synapse_model_vhdl_code.vhd" Line 69. Wait for statement unsupported.

ERROR:HDLParsers:1015 - "D:/Xilinx92i/synapse_model_final/synapse_model_vhdl_code.vhd" Line 71. Wait for statement unsupported.

Hence, I replaced the 'wait for 500 ps' statement by the sensitivity list parameters as shown below:

synapse_calc: process(adsub_out,syn_clk,adsub_in,acc_curr_out,shift_out)   

Now, the problem is:

I am not getting the same simulation waveforms in ModelSim (Figure 2 - attachment).

I am concerned that I would get totally bizzarre results while I implement synapse on the board which could be totally different from simulation. I am new to FPGA and this is my first project. Please somebody help me solve this problem with synapse so that I can proceed for other components and build the neuron.

Thanks,

A.G.Lakshmanan 

[drjohnsmith]

Hi

an age old problme this one.

Thinking hardware, how is the FPGA to impliment the 500 ps delay ?

Clue: What about a clock ?

[lakshmanan.ag]

Hello drjohnsmith,

Do you mean using an external clock to generate 500 ps delay or using another clock process? I am sorry, I did not understand.

Thanks,

A.G.Lakshmanan 

[drjohnsmith]

Hi

what I'm saying is you need to learn a HDL tool,

How are you going to generate the 500 us delay ? 

It's a fundamental differance in hardware as opposed to a computer.

You need to understand that, which means you need to understand FPGA's, which I'm afraid means you need to read up on something like VHDL.

[lakshmanan.ag]

Hello, 

I introduced a clock signal (syn_clock, frequency: 100 MHz) for triggering the process and the modified section of code is given below:

 architecture Behavioral of synapse_model_vhdl is

signal adsub_in     : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal adsub_out    : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal acc_prev_out : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal acc_curr_out : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

signal shift_out    : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

constant tau        : integer                          := 11;

signal shift_process: bit_vector(31 downto 0);

signal shift_temp   : bit_vector(31 downto 0);

begin

synapse_calc: process(syn_in,syn_clock,acc_prev_out,shift_out,adsub_out) 

begin

if syn_in = '0' then                                           

adsub_in <= "00000000000000000000000000000000";           

elsif syn_in = '1' then                                       

adsub_in <= syn_weight;                                   

end if;

if syn_clock='1' then

shift_process <= to_bitvector(acc_prev_out);    --  \\

shift_temp    <= shift_process srl tau;        -- Shifter code

shift_out     <= to_stdlogicvector(shift_temp); --  //

adsub_out <= adsub_in - shift_out;              -- Subtractor block

acc_curr_out <= acc_prev_out + adsub_out;       -- Accumulator block          

--wait for 500 ps;                                -- For simulation only

acc_prev_out <= acc_curr_out after 400 ps;

--wait for 500 ps;                                -- For simulation only

end if;

end process synapse_calc; 

syn_current <= acc_curr_out;

end Behavioral;

But, the result I get is a distorted sawtooth wave as shown in attachment(Figure 1). Please can you help?

Thanks and Regards,

 A.G.Lakshmanan

[drjohnsmith]

Ok

your learning fast, very impressed.

try looking in the simulator at the other signals you have internaly, see what they are doing and figure out if thats what you mean to do.

for instance, you don't quite have the correct format for a registered process,

A registerted process would look like

process (  syn_clock )

begin

 if rising_edge( syn_clock) then

   shift_process <= to_bitvector(acc_prev_out);

<<<< etc >>>

end if;

end process;

[eilert]

Hi,

besides the already mentioned need for understanding hardware design, here are some tips for your code:

In ISE you find  "Language Tamplates" under Edit in the menu bar (or the light bulb icon).

There you can look under VHDL and just browse the synthesis constructs for useful stuff.

This just won't work properly in synthesis. It's creating latches. 

 if syn_clock='1' then

You surely want Flipflops, which are edge triggered. So use this:

  if rising_edge(syn_clock) then

The use of the shift operator is annoying, because it's only defined for bit_vectors.

It 's nort needed anyway.

You can improve it this way:

 constant tau        : integer                          := 11;

 constant tau_zeroes : std_logic_vector (tau-1 downto 0);

and in your process:

 shift _out <= acc_prev_out(31-tau downto 0) & tau_zeroes;  -- & is the concatenation operator in VHDL

And, when you work with signals, keep in mind that you are building some pipeline structure, when you code like this.

It's ok, since you are going to work with a high clock frequency, but you have to understand that there is a latency of several clock cycles from your input to your output.

This will become important when you put together several modules, and have to care for the dataflow between these modules. 

For your model the pileline looks like this:

shift_out -> register ->  adsub_out -> register -> acc_curr_out-> register -> acc_prev_out-> register

On every rising clock edge the new calculated values are stored in the registers, so it takes four clock cycles for the values to rotate through your process.

 Still, you get new values at the output every clock cycle after the first three/four clock cycles latency.  

Remove all your "after" statements from models that are intended to be synthesized. 

Only a subset of VHDL can be synthesized. The rest is just for simulation.

 You don't need this delays anyway, since the values are delayed by the pipelining registers anyway.

Have a nice synthesis

  Eilert

[woutersj]

Just some style remarks:

Instead of writing:

signal adsub_in     : std_logic_vector(31 downto 0)    := "00000000000000000000000000000000";

you can use some shorthand such as:

signal adsub_in     : std_logic_vector(31 downto 0)    := (others => '0');

This is more maintainable. If you change the width of the vector, the zeroing will still be OK.

Another thing. Maybe you want to use signed and unsigned types instead of std_logic_vector for things like accumulators. This is a question of preference, but in general you should try to use a type that matches with the purpose.

Cheers,

Johan

[lakshmanan.ag]

Hello all,

Firstly, I would like to thank all of you for the prompt and overwhelming response ...  Thank you very very much.. !!

Following the suggestions I was able to build a synapse model. I was not able to avoid the "srl"  shift operator because the following error appeared when I used : constant tau_zeroes : std_logic_vector (tau-1 downto 0);

ERROR:HDLParsers:532 - "D:/Xilinx92i/synapse_model_final/synapse_model_vhdl_code.vhd" Line 45. Deferred constant are allowed only in packages. 

But thats okay, I have no problem with "srl". The ModelSim waveforms are fine too.. showing the good sawtooth waveforms.

Corrected code:

architecture Behavioral of synapse_model_vhdl is

signal adsub_in     : std_logic_vector(31 downto 0)    := (others => '0');

signal adsub_out    : std_logic_vector(31 downto 0)    := (others => '0');

signal acc_prev_out : std_logic_vector(31 downto 0)    := (others => '0');

signal acc_curr_out : std_logic_vector(31 downto 0)    := (others => '0');

signal shift_out    : std_logic_vector(31 downto 0)    := (others => '0');

constant tau        : integer                          := 11;

signal shift_process: bit_vector(31 downto 0);

signal shift_temp   : bit_vector(31 downto 0);

begin

synapse_calc: process(syn_in,syn_clock,adsub_in,syn_weight,acc_prev_out,shift_process,shift_temp,shift_out,adsub_out,acc_curr_out) 

begin

if syn_in = '0' then                                           

adsub_in <= "00000000000000000000000000000000";             

elsif syn_in = '1' then                                    

adsub_in <= syn_weight;                                    

end if;                                                    

shift_process <= to_bitvector(acc_prev_out);               --  \\

shift_temp    <= shift_process srl tau;                    -- Shifter code

shift_out     <= to_stdlogicvector(shift_temp);            --  //

adsub_out <= adsub_in - shift_out;                         -- Subtractor block

acc_curr_out <= acc_prev_out + adsub_out after 1 ns;       -- Accumulator block          

acc_prev_out <= acc_curr_out;

end process synapse_calc; 

syn_current <= acc_curr_out;

end Behavioral;  

Now, the problem is: Warnings !!!!

WARNING::Xst:2734 - Property "use_dsp48" is not applicable for this technology.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: Madd_acc_curr_out_cy<6>, Madd_acc_curr_out_cy<27>, Madd_acc_curr_out_cy<17>, Madd_acc_curr_out_cy<23>, Madd_acc_curr_out_cy<5>, Madd_acc_curr_out_cy<12>, syn_current<0>, Madd_acc_curr_out_cy<28>, Madd_acc_curr_out_cy<18>, Madd_acc_curr_out_cy<25>, Madd_acc_curr_out_cy<13>, Madd_acc_curr_out_cy<7>, N5, Madd_acc_curr_out_cy<2>, Madd_acc_curr_out_cy<29>, Madd_acc_curr_out_cy<19>, Madd_acc_curr_out_cy<8>, 

Madd_acc_curr_out_cy<3>, Madd_acc_curr_out_cy<1>, Madd_acc_curr_out_cy<9>, Madd_acc_curr_out_cy<14>, Madd_acc_curr_out_cy<4>, Madd_acc_curr_out_cy<30>, Madd_acc_curr_out_cy<20>, Madd_acc_curr_out_cy<24>, Madd_acc_curr_out_cy<15>, Madd_acc_curr_out_cy<10>, Madd_acc_curr_out_cy<21>, Madd_acc_curr_out_cy<0>, syn_current<31>, Madd_acc_curr_out_cy<26>, Madd_acc_curr_out_cy<16>, Madd_acc_curr_out_cy<22>, Madd_acc_curr_out_cy<11>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N35, syn_current<30>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<29>, N34.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<28>, N33.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<27>, N32.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N31, syn_current<26>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N30, syn_current<25>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<24>, N29.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<23>, N28.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<22>, N27.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<21>, N26.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N25, syn_current<20>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<19>, N24.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<18>, N23.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N22, syn_current<17>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N21, syn_current<16>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N20, syn_current<15>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<14>, N19.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<13>, N18.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<12>, N17.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N16, syn_current<11>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<10>, N15.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N14, syn_current<9>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N13, syn_current<8>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<7>, N12.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N11, syn_current<6>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N10, syn_current<5>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N9, syn_current<4>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<3>, N8.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: N7, syn_current<2>.

WARNING:Xst:2170 - Unit synapse_model_vhdl : the following signal(s) form a combinatorial loop: syn_current<1>, N6.

I tried to search for some solution but could not solve them.. Can anyone tell me what are these?

Thanks and regards,

A.G.Lakshmanan 

[drjohnsmith]

Hi

well I'm impressed at the speed your learning VHDL,

but I do think you have missed out a lot of the fundamentals,

like can I strongly suggest that you go back and have a look at how a register is constructed in VHDL. 

  do a google,

A clue, in your modelsim yousay is working, what time apart is each of the steps in the slope, I bet it's at the default resolution of modelsim, probably 1 ps.

OK, clue two. How would you get the step to be your 500 ps apart ?