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diabolique0007
Posts: 10
Registered: ‎04-29-2012
0

Signal cannot be synthesized, bad synchronous description

ERROR:Xst:827 - "T:/hamm/hamm.vhd" line 52: Signal ns1 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity lfsr is
port(
        sw:in std_logic_vector(3 downto 0);
        clk1,rst: in std_logic;
        lcd_4,lcd_5,lcd_6,lcd_7,sf_ce0,lcd_rs,lcd_rw,lcd_e:out std_logic
    );
end lfsr;
architecture arch1 of lfsr is
signal q1,q2,q3,q4:std_logic;
signal clk2: std_logic:='1';
signal o1: std_logic_vector(3 downto 0);
signal o2: std_logic_vector(7 downto 0);
type state_type is(idle,s1,s2,s3);
signal cs,ns1:state_type;
signal count:std_logic_vector(25 downto 0);
signal lcd_busy:std_logic;
signal lcd_stb:std_logic;
signal lcd_code:std_logic_vector(5 downto 0);
signal lcd_stuff:std_logic_vector(6 downto 0);
signal rw:std_logic;
signal rs:std_logic;


begin
    process(clk1)
    begin
        if(count="10111110101111000001111111")then
            count<="00000000000000000000000000";
            clk2<='1';
        elsif(count<="1011111010111100000111111")then
            clk2<='1';
            count<=count+1;
        else
            clk2<='0';
            count<=count+1;
        end if;
    end process;
    
     process(clk1)
     begin
        if(sw="0001")then
            cs<=idle;
        elsif(rising_edge(clk1))then
            cs<=ns1;
        end if;
    end process;
   
    process(clk2,cs,sw)
    variable r1,r2,r3,r4:std_logic:='1';
    begin
            
        case cs is
            
            when s1=>
                if(rising_edge (clk2)and sw<="0011")then
          
   
                r1:=r4;
                r2:= r1 xor r4;
                r3:=r2;
                r4:=r3;
        
        q1<=r1;
        q2<=r2;
        q3<=r3;
        q4<=r4;
          
                elsif(sw<="0111")then
                    ns1<=s2;
                end if;
            when s2=>
                    o1(0)<=q1;
                    o1(1)<=q2;
                    o1(2)<=q3;   
                    o1(3)<=q4;
                if(sw(3)='1')then
                    ns1<=s3;
                else
                    ns1<=idle;
                end if;
            when s3=>
                    o1(0)<=q1;
                    o1(1)<=q2;
                    o1(2)<=q3;   
                    o1(3)<=q4;
                    o2(1)<=q4 xor q2 xor q1;
                    o2(2)<=q4 xor q3 xor q1;
                    o2(3)<=q1;
                    o2(4)<=q2 xor q3 xor q4;
                    o2(5)<=q2;
                    o2(6)<=q3;
                    o2(7)<=q4;
                if(rst='1')then
                    ns1<=idle;
                end if;
                when idle=>
            if(sw<="0011")then
                ns1<=s1;
                end if;
                when others=>null;
        end case;
       
        count<=count+1;
        lcd_busy<='1';
        sf_ce0<='1';
        case count(25 downto 20) is
        when "000000" => lcd_code <= "000011";
        when "000001" => lcd_code <= "000011";
        when "000010" => lcd_code <= "000011";
        when "000011" => lcd_code <= "000010";
        when "000100" => lcd_code <= "000010";
        when "000101" => lcd_code <= "001000";
        when "000110" => lcd_code <= "000000";
        when "000111" => lcd_code <= "000110";
        when "001000" => lcd_code <= "000000";
        when "001001" => lcd_code <= "001100";
        when "001010" => lcd_code <= "000000";
        when "001011" => lcd_code <= "000001";   
        when "001100" => if(sw="0001")then
                                    lcd_code <= "100010";
                                 else
                                   lcd_code <= "100011";
                                end if;
        when "001101" => if(sw="0001")then
                            
                                    lcd_code <= "100000";
                              elsif(sw="0011")then
                                   
                                  lcd_code <= "10000"& q4;
                              elsif(sw="0111" and sw="1111")then       
                                    lcd_code <= "10000"& o1(3);
                                        else
                                             lcd_code<="100000";    
                           end if;
        when "001110" => if(sw="0001")then
                                    lcd_code <= "100010";
                                 else
                                   lcd_code <= "100011";
                                 end if;
        when "001111" => if(sw="0001")then
                                   
                                    lcd_code <= "100000";
                              elsif(sw="0011")then
                                 
                                    lcd_code <= "10000"& q3;
                              elsif(sw="0111" and sw="1111")then
                                    lcd_code <= "10000"& o1(2);
                                        else
                                             lcd_code<="100000";            
                              end if;   
        when "010000" => if(sw="0001")then
                                    lcd_code <= "100010";
                                 else
                                   lcd_code <= "100011";
                                 end if;
        when "010001" => if(sw="0001")then
                                    lcd_code <= "100000";
                                   
                              elsif(sw="0011")then
                                  lcd_code <= "10000"& q2;
                                   
                              elsif(sw="0111" and sw="1111")then
                                    lcd_code <= "10000"& o1(1);
                                        else
                                             lcd_code<="100000";    
                              end if;        
        when "010010" => if(sw="0001")then
                                    lcd_code <= "100010";
                                 else
                                   lcd_code <= "100011";
                                 end if;
        when "010011" => if(sw="0001")then
                                    lcd_code <= "100000";
                                   
                              elsif(sw="0011")then
                                  lcd_code <= "10000"& q1;
                              elsif(sw="0111" and sw="1111")then
                                  lcd_code <= "10000"& o1(0);
                                        else
                                            lcd_code<="100000";    
                              end if;
        when "010100" => lcd_code <= "001100";
        when "010101" => lcd_code <= "000000";
        when "010110" =>if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "010111" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(7);
                              else
                                  lcd_code <= "100000";
                              end if;
        when "011000" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "011001" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(6);
                              else
                                  lcd_code <= "100000";
                              end if;
        when "011010" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "011011" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(5);
                              else
                                  lcd_code <= "100000";
                              end if;
        when "011100" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "011101" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(4);
                              else
                                  lcd_code <= "100000";
                              end if;
        when "011110" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "011111" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(3);
                              else
                                  lcd_code <= "100000";
                              end if;
        when "100000" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "100001" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(2);
                              else
                                  lcd_code <= "100000";   
                       end if;                                   
        when "100010" => if(sw="1111")then
                                    lcd_code <= "100011";
                                 else
                                   lcd_code <= "100010";
                                 end if;
        when "100011" => if(sw="1111")then
                                    lcd_code <= "10000"& o2(1);
                              else
                                  lcd_code <= "100000";                           
                              end if;        
                                   
                                   
        when others => lcd_code<="010000";
        end case;
        lcd_stb<= (count(19)xor count(18)) and ((not rw) and lcd_busy);
        lcd_stuff <= lcd_stb & lcd_code;
        lcd_e <= lcd_stuff(6);
        rs <= lcd_stuff(5);
        rw <= lcd_stuff(4);
        lcd_7 <= lcd_stuff(3);
        lcd_6 <= lcd_stuff(2);
        lcd_5 <= lcd_stuff(1);
        lcd_4 <= lcd_stuff(0);
        end process;
        lcd_rw<=rw;
        lcd_rs<=rs;

end arch1;

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: Signal cannot be synthesized, bad synchronous description

[ Edited ]

I do not use VHDL for design, but I can read VHDL well enough to see that you are just beginning to learn VHDL.

 

If you want to learn VHDL on your own, you should purchase a decent VHDL textbook.  You should read the NEW USERS README and FAQ (a shameless self-promotion) here, which includes some links for textbook recommendations.

 

You can also learn much from the ISE Language Templates examples.  Simply click on the 'light bulb' icon in the ISE Navigator.

 

A suggestion for using the trial-and-error learning approach:  Implement (add or change) and test just one new coding construct at a time, so you can readily tell which lines of your code are provoking synthesis errors.

 

For example:

 

  • You have written code which describes several processes in your posting, and you aren't sure which process(es) are provoking the error message.
  • So comment out all but one or two processes in your code, and debug one at a time, so you learn one code construction lesson at a time.
  • If you make small changes in each step, you have a much better idea where to look when new error messages appear or disappear.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor
diabolique0007
Posts: 10
Registered: ‎04-29-2012
0

Re: Signal cannot be synthesized, bad synchronous description

Though I'm new to VHDL i'm have already followed the procedures of debugging which u have mentioned.... I just can't figure out why the error pops up
Expert Contributor
hgleamon1
Posts: 857
Registered: ‎11-14-2011

Re: Signal cannot be synthesized, bad synchronous description

[ Edited ]

Hello,

 

I agree with everything that Bob wrote. There is a lot going on here and I have not had the time to go through the whole text but, these are the first things that jumped out at me:

 

process(clk1)

begin

  if(count="10111110101111000001111111") then

    count<="00000000000000000000000000";

    clk2<='1';

  elsif(count<="1011111010111100000111111") then

    clk2<='1';

    count<=count+1;

  else

    clk2<='0';

    count<=count+1;

  end if;

end process;

 

You have a process that uses clk1 in the sensitivity list but then doesn't use it. This is now a combinatorial process. You are also trying to create a clock divider. These are not so good in combinatorial processes. Use clk1 to synchronise the assignments.

 

Further, consider your comparator:

 

if(count="10111110101111000001111111") then

If the counter is EQUAL to this value ..



elsif(count<="1011111010111100000111111") then

if the counter is LESS THAN OR EQUAL to the same value ..

 

How can these conditions ever be different? clk2 will always be '1', surely?

 

process(clk2,cs,sw)

  variable r1,r2,r3,r4:std_logic:='1';

begin 

  case cs is

    when s1=>

      if(rising_edge (clk2)and sw<="0011")then

 

Now you are trying to use the divided clock as a clock. This is not good design practice. It would be better to keep clk1 as the main clock and use clk2 as a clock enable, as clk2 is a logic signal, not a clock signal. Plus, you should consider how your process is synchronised. For example:

 

process (clk1,sw)

  variable r1,r2,r3,r4:std_logic :='1';

begin

  if rising_edge(clk1) then -- synchronising clock

    if ((clk2 = '1') and (sw <="0011)) then -- clock enable

 

Do you really mean sw <= "0011"? Less than or equal? May be you do but I'm just checking.

 

Finally, for this comment at least, you should consider giving your signals meaningful names (especially FSM states) and using comments in your code. I really have no idea what you are trying to achieve.

 

Regards,

 

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle
Expert Contributor
gszakacs
Posts: 5,253
Registered: ‎08-14-2007

Re: Signal cannot be synthesized, bad synchronous description

In your state process you have:

 

when s1=>
  if(rising_edge (clk2)and sw<="0011")then
    . . .
  elsif(sw<="0111")then
    ns1<=s2;
  end if;

 

First of all, a process should either be synchronous and have the "if rising_edge(clk2)" as the outermost

if statement, or fully combinatorial.  This process seems to be a little of each.

 

How do you interpret the elsif clause?  It seems to depend on "not rising_edge(clk2)"

I'm not sure what the synthesizer will do with that...

 

-- Gabor

-- Gabor
Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: Signal cannot be synthesized, bad synchronous description

Though I'm new to VHDL i'm have already followed the procedures of debugging which u have mentioned.... I just can't figure out why the error pops up

 

If you had followed the described debugging procedures correctly, you would not be posting as much code as you did, or with as many processes as it includes.  You would have posted code with a single process -- one which provokes the error -- and sufficient port definitions to prevent "trimming" of the process logic from the design.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Xilinx Employee
herver
Posts: 97
Registered: ‎08-17-2011

Re: Signal cannot be synthesized, bad synchronous description

Hello diabolique0007


process(clk1)

begin

  if(count="10111110101111000001111111") then

    count<="00000000000000000000000000";

    clk2<='1';

  elsif(count<="1011111010111100000111111") then

    clk2<='1';

    count<=count+1;

  else

    clk2<='0';

    count<=count+1;

  end if;

end process;

You should have use decimal values, like 49999999, and 24999999 to avoid wasting your time and most importantly when asking for advices, those trying to help you... it would have been obvious that the constants are different!
Since in you code, it looks like you care only when clk2 is changing from 0 to 1, then the following code should be appropriate - please note that advices like don't generate clocks like you do still apply! - :

 

process(clk1) begin
  if(rising_edge(clk1)) then
    if(count=49999999)then
      clk2_ena<='1';
      count<=(others => '0');
    else
      clk2_ena<='0';
      count<=count+1;
    end if;
  end if;
end process;

- Hervé
Expert Contributor
hgleamon1
Posts: 857
Registered: ‎11-14-2011
0

Re: Signal cannot be synthesized, bad synchronous description

You should have use decimal values, like 49999999, and 24999999

 

OK, they are not the same number. Well spotted. Too many binary characters for my eyes!

 

Regards,

 

Howard



----------
"That which we must learn to do, we learn by doing." - Aristotle