Synthesis

[atashsa_b]

hello.how can I solve it?
I want when the process is started the signal "stop_internal='1' and when it finished signal "stop_internal ='0' ,but this error is occured?
Signal stop_internal cannot be synthesized, bad synchronous description

Code:

process(clk,reset,clk_external,clr_in)
    variable  i:integer range 0 to 8;
    variable col_index_nonzero_i:integer range 1 to 2304;
    variable a:integer range 0 to 1;
    variable stop_internal:bit;
    begin 
      if reset ='1' then 
        i:=0;
      else
        if (clr_in'event and clr_in='1') then
          stop_internal:='1';
        end if;
         if (clk'event and clk='1')and (stop_internal='1') then 
          if i=length_row then
           i:=1;
           stop_internal:='0';
           i:=1;
          else
            i:=i+1;
          end if;
			    if b>0 then 
            a:=1;
          else
            a:=0;
          end if;
end if;
end if;
end process;

[rcingham]

Your code is attempting to infer both 'clr_in' and 'clk_in' as clocks.
Probably not what you want.
Time to take a course or buy a textbook.

[bassman59]

Wow, there are tons of things wrong with your process. As ryan says, buy a textbook and take a course.

Your process uses two clocks, which is ridiculous, because no FPGA flip-flops have two clock inputs. 

Also, the process doesn't assign to any signals, and as such has no outputs, so it'll all get optimized out by the tools.

[atashsa_b]

thank you, what am I doing? I want this program to be implemented when the previous program was runned,so I use a signal  be '1' when the previous program ended and when this signal event and be '1' the current program run

[rcingham]

> thank you, what am I doing?

Failing to understand the nature of the target hardware.
Your Hardware Description Language (HDL) code must describe something that can be mapped onto the target hardware. This can be quite difficult for people used to writing software.

[bassman59]

---

atashsa_b wrote:

thank you, what am I doing? I want this program to be implemented when the previous program was runned,so I use a signal  be '1' when the previous program ended and when this signal event and be '1' the current program run

---

You need to THINK HARDWARE.

You are thinking software.

You should take a series of classes in synchronous digital circuit design before attempting an FPGA design, because FPGA design IS synchronous digital circuit design.

The fact that VHDL "looks" kinda sorta almost like a programming language is purely coincidental.

[eteam00]

The fact that VHDL "looks" kinda sorta almost like a programming language is purely coincidental.

I don't think it's coincidental at all.

In the 1980s, the C language crowd was quite certain that

• hardware logic design is no different than software design

• software designers were smarter and more efficient than hardware designers

• at the end of the day, hardware logic design is best done by software designers rather than their overpaid, C-language-challenged gate-obsessed hardware design colleagues.

25 years on, we're still here...  :)

-- Bob Elkind

[rcingham]

> The fact that VHDL "looks" kinda sorta almost like a programming language is purely coincidental.

Actually, it's syntax is derived from that of Ada, the USA DoD's software programming language. That probably seemed like a really good idea at the time, but as we now realise, there are some down-sides...

[bassman59]

---

rcingham wrote:
> The fact that VHDL "looks" kinda sorta almost like a programming language is purely coincidental.

Actually, it's syntax is derived from that of Ada, the USA DoD's software programming language. That probably seemed like a really gpood idea at the time, but as we now realise, there are some down-sides...

---

Downsides? 

such as?

[rcingham]

---

bassman59 wrote:

---

rcingham wrote:
> The fact that VHDL "looks" kinda sorta almost like a programming language is purely coincidental.

Actually, it's syntax is derived from that of Ada, the USA DoD's software programming language. That probably seemed like a really good idea at the time, but as we now realise, there are some down-sides...

---

Downsides? 

such as?

---

Some people mislead themselves to think that because it looks somewhat like a programming language that a similar paradigm applies, then get cross/unhappy when they find it doesn't, at least for HDL that has to be fed into a synthesizer.