Signal x cannot be synthesized, bad synchronous description.

cosmoron · ‎05-18-2012

Hi,

First of all I want to say that I'm aware of the fact that this is a common problem and there are a lot of topics on this.

But I've spent the entire day reading them and trying to apply it to my problem with no result. I've read the newbie guide.

Believe me, I'VE TRIED.

I have to design a code which gives me a signal with 1.1sec in HIGH and the rest of the time stays 0.

My entity and behavioral works fine in model sim but it s ridiculously wrong when it comes to synthesize.

Here s the code:

entity clkdiv is port ( CLK: in std_logic; CLKOUT: out std_logic; PB : in std_logic ); end clkdiv; architecture DIV of clkdiv is signal MAXCOUNT: std_logic_vector (22 downto 0):= "00000000001010101111100"; signal COUNT: std_logic_vector (22 downto 0):= (others =>'0'); begin process(CLK) variable PUSHBUTTON: integer; begin if (PB='1')then PUSHBUTTON:= 1; end if; if (PUSHBUTTON = 1) then if(rising_edge (CLK)) then if(COUNT < MAXCOUNT ) then COUNT <= COUNT+1; CLKOUT <= '1'; elsif (COUNT=MAXCOUNT) then COUNT <= (others => '0'); CLKOUT <= '0'; PUSHBUTTON:=0; end if; end if; elsif COUNT <= (others => '0'); CLKOUT <= '0'; end if; end process; end DIV;

ERROR:Xst:827 Signal PUSHBUTTON cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

I dont have elses in rising_edge..

PB is my RESET button. So when i press it I want to get the 1.1sec high.

I know it s easy and you re tired of this, but I am new and I cant find a solution.

bassman59 · ‎02-25-2008

The XST Synthesis and Style guide should have been the first FM you read.

Synthesis basically involves template matching and logic minimization. So your code must match the expected templates or else the tools barf.

Your code doesn't match any of the templates. Your sensitiviity list includes only the clock, which is correct for a synchronous process with a synchronous reset. However, you don't actually code the synchronous reset. You code (clumsily) an asynchronous reset.

What's the difference?

The synchronous reset is tested within the block of the if rising_edge(clk) then ... as such:

SyncReset : process (clk) is

begin

if rising_edge(clk) then

if reset = '1' then

q <= '0';

else

if (foo = '1') then

q <= bar;

else

q <= bletch;

end if;

end process SyncReset;

The asynchronous reset is tested before the clock edge is checked, and the reset must be listed on the senstivity list (otherwise, in simulation, the process will never be triggered by a change in the reset signal):

AsyncReset : process (clk, reset) is

begin

if reset = '1' then

q <= '0';

elsif rising_edge(clk) then

if (foo = '1') then

q <= bar;

else

q <= bletch;

end if;

end process AsyncReset;

Do you see the difference? And note that you have to do the elsif rising_edge(clk) here for the template to recognize the async reset.

----------------------------------------------------------------
Yes, I do this for a living.

bassman59 · ‎02-25-2008

Plus, also, one more time for the world:

a) your counter signal should NOT be declared as a std_logic_vector. It should be an integer or a natural (no negative numbers. And it should have a range associated with it.

So assume your clock is 10 MHz, or 100 ns period. To count to 1.1 seconds, you need to count to 11 million.

Do this:

constant ELEVENMILLION : natural = 11000000;

signal count : natural range 0 to ELEVENMILLION - 1 := 0; -- because you count from 0

Count1p1sec : process (clk) is

begin

if rising_edge(clk) then

if pb = '1' then

count <= ELEVENMILLION - 1;

elsif count > 0 then

count <= count - 1;

end if;

if (count /= 0) then

clkout <= '1';

else

clkout <= '0';

end if;

end process Count1p1sec;

Quite simple, eh?

----------------------------------------------------------------
Yes, I do this for a living.

cosmoron · ‎05-18-2012

But I did that because I saw it in school that an integer count produced an error when synthesizing.. So the teacher said we should you std_logic and make it binary. I am going to try your way tomorrow and I really hope it s going to work. Well, considering your experience I'm pretty sure it will. But I m wondering what will happen when counter reaches 0.

What value will clockout have. I'm gonna see.

The other thing that bugged me was that in the RTL schematic I didnt have this entity. But I'm hoping now it will appear.

WARNING:Xst:1290 - Hierarchical block <Inst_clkdiv> is unconnected in block <system>.
It will be removed from the design.

But in system I have:
...
COMPONENT clkdiv
PORT(
CLK : IN std_logic;
PB : IN std_logic;
CLKOUT : OUT std_logic
);
END COMPONENT;
..
Inst_clkdiv: clkdiv PORT MAP(
CLK =>CLOCK,
CLKOUT => sig1 ,
PB => RESET
);

Is it possible that the problem is that I use the same clock for two entities?

COMPONENT clkdiv4
PORT(
CLK : IN std_logic;
CLK800HZ : OUT std_logic
);
END COMPONENT;
Inst_clkafisare: clkdiv4 PORT MAP(
CLK => CLOCK,
CLK800HZ => sig2
);

Thank you again.

cosmoron · ‎05-18-2012

Nevermind this:
"But I m wondering what will happen when counter reaches 0."

It s clearly that when counter reaches 0 stays in 0 and clkout stays in 0.
if (count /= 0) then

clkout <= '1';

else

clkout <= '0';

end if;
I'm tired and i missed it.

Thank you.

cosmoron · ‎05-18-2012

I could not wait untill tomorrow so I've tried your solution now, even though it's 3 a.m. here.
It works but it has a small issue:

if rising_edge(clk) then
if pb = '1' then
count <= ELEVENMILLION - 1;

You can see here that if the pb HIGH last for .. lets say 50 rising_edges of clock then count will be initializated to ELEVENMILLION - 1; 50 times instead of decreasing.

This is the closest I got so far: 1.1sec - 1*period of clock .
constant MAXCOUNT : integer := 5500 ;
signal count, countpb: integer range 0 to MAXCOUNT := 0;

begin
Count1p1sec : process (clk) is
begin
if rising_edge(clk) then
if PB = '1' then
count <= MAXCOUNT;
countpb<=countpb+1;
elsif count > countpb then
count <= count-1;
end if;

if (count /= countpb) then
CLKOUT <= '1';
else
CLKOUT <= '0';
end if;

end if;

end process;
end Behavioral;

The problem is that i dont know how to get the countpb back to 0 on every reset..

cosmoron · ‎05-18-2012

Sorry for the multiposts, I dont see an edit button :)

UPDATE: Problem solved (I guess) final code looks like this:

entity clkdiv is
   port (
       CLK: in std_logic;
       CLKOUT: out std_logic;
      PB : in std_logic
   );
end clkdiv;

architecture Behavioral of clkdiv is

constant MAXCOUNT : integer := 5500 ;
signal count, countpb: integer range 0 to MAXCOUNT := 0;

begin
    Count1p1sec : process (clk) is
    begin
        if rising_edge(clk) then
            if PB = '1' then
                count <= MAXCOUNT-countpb-1;
                countpb<=countpb+1;
            elsif count > 0 then
                 count <= count-1;
            end if;

            if (count /= 0) then
               CLKOUT <= '1';
            else
                CLKOUT <= '0';
                countpb<= 0;
            end if;

        end if;

    end process;
end Behavioral;

Thanks. Now I have to deal with this:

WARNING:Xst:737 - Found 1-bit latch for signal <sig8_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 4-bit latch for signal <sdot>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <1>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <0> has a constant value of 1 in block <2>. This FF/Latch will be trimmed during the optimization process.

INFO:Xst:2261 - The FF/Latch <sdot_0> in Unit <system> is equivalent to the following FF/Latch, which will be removed : <sdot_2>
WARNING:Xst:1293 - FF/Latch <sdot_0> has a constant value of 1 in block <system>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <sdot_1> has a constant value of 0 in block <system>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <Inst_osc2bit/Q_0> in Unit <system> is equivalent to the following FF/Latch, which will be removed : <Inst_osc2bit/S0>
INFO:Xst:2261 - The FF/Latch <Inst_osc2bit/Q_1> in Unit <system> is equivalent to the following FF/Latch, which will be removed : <Inst_osc2bit/S1>

At least there are no errors :)

LATER EDIT : SOLVED the underlined text.

INFO:Xst:2261 - The FF/Latch <Inst_osc2bit/Q_0> in Unit <system> is equivalent to the following FF/Latch, which will be removed : <Inst_osc2bit/S0>
INFO:Xst:2261 - The FF/Latch <Inst_osc2bit/Q_1> in Unit <system> is equivalent to the following FF/Latch, which will be removed : <Inst_osc2bit/S1>

This are the only two things left. Will it be a problem? From what I can understand it has two similar FF/Latch and it keeps just one and use it for both cases. I dont see why this would be a problem.

cosmoron · ‎05-18-2012

Well, now that I already have the topic open I might as well tell my other problems.

My synthesize works fine now but i have some warnings that I m pretty sure they going to affect my final project.

I'm using the internal 50MHZ clock of my FPGA as clock for my entire system and I just linked the CLOCK to the pin on the board as you can see here:

NET "CLOCK" LOC = T9;
NET "dots" LOC = P16;
NET "RESET" LOC = L14;
NET "result[6]" LOC = E14;
NET "result[5]" LOC = G13;
NET "result[4]" LOC = N15;
NET "result[3]" LOC = P15;
NET "result[2]" LOC = R16;
NET "result[1]" LOC = F13;
NET "result[0]" LOC = N16;
NET "anod[3]" LOC = E13;
NET "anod[2]" LOC = F14;
NET "anod[1]" LOC = G14;
NET "anod[0]" LOC = D14;

Ok, now i get this warnings:

MAP

WARNING:PhysDesignRules:372 - Gated clock. Clock net impuls is sourced by a    combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.


PLACE AND ROUTE


WARNING:Route:455 - CLK Net:Inst_BCD_Counter_unitati/carry may have excessive skew because
      3 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:impuls may have excessive skew because
      3 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:Inst_BCD_Counter_zecimale/carry may have excessive skew because
      3 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
WARNING:Route:455 - CLK Net:Inst_clkafisare/DIV may have excessive skew because
      0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Now, is this the proper way to use the CLOCK or how am I supossed to do it?

hgleamon1 · ‎11-14-2011

1. This is not related to your original problem, so you should have started a new thread (particularly as this thread is marked as solved!). However, I'll run with it.

2. You haven't really given an indication (in this last post) as to how the physical pin CLOCK relates to the internal signal "implus". However, I'm going to take an educated guess that it comes from your clock divider mentioned in previous posts on this thread. If I'm wrong, I apologise in advance and request that you give us more details of this signal.

You must, and I mean MUST, try to understand that your clock divider produces a LOGIC signal that is routed in the FPGA in logic resource. It is fundamentally bad design practice to use this divided signal AS A CLOCK. The silicon and the tools are really not set up to handle this but they can manage it (hence the warning).

You should be using your divided signal as a CLOCK ENABLE (hence the warning saying use the CE pin to load the FF). A clock enable is coded like this:

A_PROCESS : process (clock)

begin

if rising_edge(clock) then -- main clock signal, routed from clock resources

if (clock_enable = '1') then -- the clock enable, possibly from a clock divider process

-- logic statements

else

-- other logic statements, if necessary

end if;

end process A_PROCESS;

I hope this helps.

Regards,

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle

bassman59 · ‎02-25-2008

cosmoron wrote:
I could not wait untill tomorrow so I've tried your solution now, even though it's 3 a.m. here.
It works but it has a small issue:

if rising_edge(clk) then
if pb = '1' then
count <= ELEVENMILLION - 1;

You can see here that if the pb HIGH last for .. lets say 50 rising_edges of clock then count will be initializated to ELEVENMILLION - 1; 50 times instead of decreasing.

Then you need a simple edge detector. Syncronize pb to the clock, call the output of the synchronizing flop pb_s. Then delay the synchronized signal pb_s with another flip-flop; call it pb_d. The rising edge on pb occurs when the delayed flop pb_d is '0' and the new synchronized pb_s is '1'. Of course this ignores debouncing which is probably necessary.

This rising edge indicator strobe will be true for exactly one clock tick. Use it as the counter load enable.

----------------------------------------------------------------
Yes, I do this for a living.