Synthesis

[head_up]

Hi! i was read a long time ago: Xilinx ISE will support SystemVerilog in v10. ok, now we have 11.3 (must update to 11.4) but SystemVerilog still "out of range". Can i expect ISE 12 to support SV for synthesis or i must look around for other (too expensive) tools like Synplify Pro? I'm sorry if my question is tedious, but i realy need to know what is the true way for the design tools and fature support of SV language by Xilinx. i must make a choice for near feature designs and the time passes.

[siktapany]

SystemVerilog is not planned for support in 12.1.

[gjoli]

Switch to Altera + Quartus.

SystemVerilog (as well as VHDL 2008) is supported since quite a few versions in Quartus ;-)

[brucey]

I believe SV support is on the way now.

[pbeerak]

Is SystemVerilog supported in ISE12.3 

[patelb1]

Any official reply from Xilinx on when system verilog support is coming to XST?

[gr_smurf]

I noticed in ISE 13.1 quite a few systemverilog constructs do get syntax highlighted in the editor ... but trying to use those still gets a syntax error.

It looks like some parts of ISE is getting worked on for SystemVerilog. Any news on what kind of SystemVerilog support to expect first in ISE?

[jlqsczw_2007]

I am also concerned about this issue frevently.

[viviany]

System Verilog will not be supported in ISE. It will be supported in the next generation software which will be released in the second half of 2012.

Vivian

[kaushalmodi]

Hi, it's 2013 now, I am using Xilinx 14.4. I still don't think the ISE is supporting System Verilog. Is it? If so, how can I enable it?

Thanks