02-27-2010 06:22 AM
04-28-2011 10:43 PM
I noticed in ISE 13.1 quite a few systemverilog constructs do get syntax highlighted in the editor ... but trying to use those still gets a syntax error.
It looks like some parts of ISE is getting worked on for SystemVerilog. Any news on what kind of SystemVerilog support to expect first in ISE?