Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Newbie
wszelago
Posts: 1
Registered: ‎07-10-2012
0

VHDL - FF/Latch problem

Hi,

 

How to correct warnings:

WARNING:Xst:1426 - The value init of the FF/Latch FFd2 hinder the constant cleaning in the block FSM.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch FSM_FFd2 hinder the constant cleaning in the block FSM_0-parent.
You should achieve better results by setting this init to 1.

 

What does it mean exactly? As simple as possible please:)

 

Kind regards,

W

Expert Contributor
bassman59
Posts: 6,177
Registered: ‎02-25-2008
0

Re: VHDL - FF/Latch problem

[ Edited ]

wszelago wrote:

Hi,

 

How to correct warnings:

WARNING:Xst:1426 - The value init of the FF/Latch FFd2 hinder the constant cleaning in the block FSM.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch FSM_FFd2 hinder the constant cleaning in the block FSM_0-parent.
You should achieve better results by setting this init to 1.

 

What does it mean exactly? As simple as possible please:)

 

Kind regards,

W


It means that the tools are too stupid to breathe.

 

I always see this when I use a short shift register to generate a synchronous reset (or the async reset into a DCM). Something like this:

 

    signal rst_sr : std_logic_vector(3 downto 0) := (others => '1');

    alias SReset : std_logic is rst_sr(3);

 

    CreateReset : process (clk) is

    begin

        if rising_edge(clk) then

            rst_sr <= rst_sr(2 downto 0) & '0';

        end if;

    end process CreateReset;

 

The tools correctly initialize rst_sr to all '1', and the shift register works too, but there's always the complaint about hindered constant clearing.

 

I just ignore the warning.


----------------------------------------------------------------
Yes, I do this for a living.
Expert Contributor
gszakacs
Posts: 7,014
Registered: ‎08-14-2007
0

Re: VHDL - FF/Latch problem

Well, the tools are really saying that if your register was initialized to all zero, it could be

replaced by logic because it would never be anything but zero.  Of course if that were

the case, then you'd not only get rid of the intent of the design (to have a usable reset)

but you'd also pick up another warning saying that sequential register rst_sr has a

constant value of 0000 and it will be replaced by logic.

 

So the real moral of this story is that you'll never get rid of all the messages in XST.

 

-- Gabor

-- Gabor
Xilinx Employee
sauravs
Posts: 100
Registered: ‎08-14-2012
0

Re: VHDL - FF/Latch problem

Hi,

 

This warning occurs when a register with an INIT value (the initialization value that a memory element has when the FPGA is powered on) has a constant input that does not match the INIT value and no other control signal (such as a local set/reset). The constant input might be due to an undriven input or logic optimization.  

 

To avoid the warning, examine the logic value and/or trimming at the input signal of the register. If the values of the input and INIT match, XST will be able to optimize the registers using constant optimization. 

 

For more information on inferring INIT values in HDL, please refer to  http://www.xilinx.com/support/answers/15149.htm

 

regards,

saurav

 

Expert Contributor
bassman59
Posts: 6,177
Registered: ‎02-25-2008
0

Re: VHDL - FF/Latch problem

[ Edited ]

sauravs wrote:

Hi,

 

This warning occurs when a register with an INIT value (the initialization value that a memory element has when the FPGA is powered on) has a constant input that does not match the INIT value and no other control signal (such as a local set/reset). The constant input might be due to an undriven input or logic optimization.  


Except it's a stupid warning. 

 

The VHDL initializer should be the INIT value. A reset clause in the process would be redundant and not necessary, especially if there's no explicit external reset.  (An initializer which assigns one value to the signal and a reset which assigns the opposite value actually is cause for concern and some very interesting warnings and logic result.)

 

The example I give works and I use it in pretty much every design I've done. It is used to generate a synchronous reset of some known width after configuration. It is also Xilinx' suggested method of resetting DCMs.


----------------------------------------------------------------
Yes, I do this for a living.