Dear all ,
I have managed to finish all the blocks for my router algorithm and I am now trying to run a XST synthesis on ISE webpack and I am facing a problem that I cannot understand how to solve!
I am using a specific block 5 times and have declared some signals for each one of these.
I ve used the same technique for all of them and when I run the XST to see the blocks connected all of them seem connected exept some ports of one of them.
I mean I ve done the same exaxt actions for all 5 and written the code for the specific one again but could not solve the problem!
Is there a possibility that because I am using the webpack I cannot make a full synthesis?
When connecting signals with in/out ports of the components like this : in=> in_signal you dont have to keep order in declaring inputs first and then outputs right?
