Synthesis

[skinwalker00]

Hello,

I'm trying to build a simple CPU for a school assignment. It has a very very basic ISA. The code is below. My issue is that I am getting this warning: "WARNING:Xst:1781 - Signal <IMEM> is used but never assigned. Tied to default value." when I try to Synthesize. IMEM is the code that drives my program so this is not good.

I'm brand new to Verilog and have spent a fair amount of time trying to solve this problem. If I comment out where IMEM is used (in the fetch stage) then the error changes to Signal<IMEM> is assigned but is never used.

For the record, this program simulates exactly as expected. It just doesn't work when I throw it into a FPGA

Here is my code: (I've also attached the project file)

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:44:31 06/20/2012
// Design Name:
// Module Name: CPU
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CPU(clk,bus
);

input clk; // system clock
output reg [7:0] bus;

// The ISA
parameter fetch = 2'b00;
parameter decode = 2'b01;
parameter execute = 2'b10;

// op codes
//////////////////////////////////////////////////////////////////////////////////////////////////////////
parameter LDA = 3'b000; // Loads the contents of memory address into accumulator

parameter STA = 3'b001; // Store contents of accumulator into memory address

parameter ADD = 3'b010; // Add contents of memory address to contents of the accumulator
// and stores the result in accumulator

parameter SUB = 3'b011; // Subtracts contents of memory address to contents of the accumulator
// and stores the result in accumulator

parameter OUT = 3'b100; // Output contents of accumulator to external data bus (i.e. LED lights)

parameter SHL= 3'b101; // Shift Left contents of accumulator and fill LSB with zero.
// Store result in accumulator .

parameter JMP = 3'b110; // Load memory address into program counter. This causes a jump to that address

parameter HLT = 3'b111; // Halts program execution
////////////////////////////////////////////////////////////////////////////////////////////////////////

reg[7:0] IMEM[31:0]; // Our instruction memory
reg[7:0] AC = 0; // accumulator
reg[7:0] IR = 0; // Instruction Register
reg[7:0] MEM[31:0];

reg[1:0] current_state;
reg[1:0] next_state;
reg[4:0] PC; // progam counter
reg [2:0] opcode;
reg [4:0] operand;
integer i;

// Boot up
initial begin
bus = 0;
current_state = 0;
next_state = 0;
PC = 0; // progam counter
opcode = 0;
operand = 0;

// initialize Memory
for (i = 0; i < 32; i = i + 1)begin
MEM[i] = i;
end
// A simple program that takes into account all of our op-codes
//
//Load Data from mem address 2 (which is a 2) and display

IMEM[0] = {LDA, 5'b00010};
IMEM[1] = {OUT, 5'b00000};
// ADD 2 to Accum -> Store value in Address 0 -> Load from address 3(to "clear" the value)->
// Load address 0 back in (should be 4) -> display
IMEM[2] = {ADD, 5'b00010};
IMEM[3] = {STA, 5'b00000};
IMEM[4] = {LDA, 5'b00011};
IMEM[5] = {LDA, 5'b00000};
IMEM[6] = {OUT, 5'b00000};
// Sub 1 from Accum -> Store in Address 25 -> Load from address 1 (to "clear" the value) ->
// Load address 25 back in -> display (should be a 3)
IMEM[7] = {SUB, 5'b00001};
IMEM[8] = {STA, 5'b11001};
IMEM[9] = {LDA, 5'b00001};
IMEM[10] = {LDA, 5'b11001};
IMEM[11] = {OUT, 5'b00000};
// Shift Accum Right -> Display (Should be 6)
IMEM[12] = {SHL, 5'b00000};
IMEM[13] = {OUT, 5'b00100};
// Jmp PC to 17 -> (Skip the add and display) -> and then halt (which means the next add and display will
// never be done -> So display should never change from 6
IMEM[14] = {JMP, 5'b10001};
IMEM[15] = {ADD, 5'b00001};
IMEM[16] = {OUT, 5'b00000};
IMEM[17] = {HLT, 5'b00000};
IMEM[18] = {ADD, 5'b00001};
IMEM[19] = {OUT, 5'b00000};
IMEM[20] = 'b00000000;
IMEM[21] = 'b00000000;
IMEM[22] = 'b00000000;
IMEM[23] = 'b00000000;
IMEM[24] = 'b00000000;
IMEM[25] = 'b00000000;
IMEM[26] = 'b00000000;
IMEM[27] = 'b00000000;
IMEM[28] = 'b00000000;
IMEM[29] = 'b00000000;
IMEM[30] = 'b00000000;
IMEM[31] = 'b00000000;
end

// State Machine
always @(posedge clk)
begin

case(current_state)
fetch: begin
// fetch instruction from instruction memory
IR = IMEM[PC];
next_state = decode;
end

decode: begin
// decode the instruction
PC = PC + 1;
next_state = execute;
opcode = IR[7:5];
operand = IR[4:0];
end

execute: begin
// excute the instruction
// see opcode declerations for more details
// on individual opcodes
case (opcode)
LDA:begin
AC = MEM[operand];
next_state = fetch;
end

STA: begin
MEM[operand] = AC;
next_state = fetch;
end

OUT: begin
for ( i = 0; i < 8; i = i+1)
begin
bus[i] = AC[i];
end
next_state = fetch;
end

ADD: begin
AC = AC + MEM[operand];
next_state = fetch;
end

SUB: begin
AC = AC - MEM[operand];
next_state = fetch;
end

SHL: begin
AC = {AC[6:0],1'b0};
next_state = fetch;
end

JMP: begin
PC = operand;
next_state = fetch;
end

HLT: begin
// loop forever
next_state = execute;
end

default
begin
// Should never happen
end
endcase
end
default: begin
// should never happen
// but try to recover
next_state = fetch;
end
endcase

// move to next state
current_state = next_state;
end
endmodule

[bassman59]

Looks like you've confused synthesizable code and simulation code.

[skinwalker00]

As I said I'm brand new to Verilog. I don't want to sound ungrateful, but your reply is very ambiguous. What do you mean I've confused synthesizable code and simulation code? Could you point me in the right direction?  

From what you said maybe I need to split my states to not do as much in one clock cycle? I'm really not sure what I'm doing wrong.

Justin

[gszakacs]

It is very likely that this warning is a red herring, and not your problem.  XST throws this warning

if a signal is never assigned other than during initialization.  So it doesn't mean thar the initialization

within the initial block did not happen.

Your code is very hard to read without any indentation.  You might try to attach it as a file

if you want more help.

-- Gabor

[skinwalker00]

Thanks for the reply Gabor.

I did attach the entire project file in my first post but have reattached my code as a text file.

That's a good point that it may be false warning by Xilinx.  I have the "BUS" tied to some LEDs on the Spartan FPGA board. The output is sporadic. I can't figure out anything else that is wrong with my code so I was trying to figure out what this error is as it may be causing it.

Justin 

[gszakacs]

Some comments on the code:

1) You have no reset input or reset terms.  The only initialization is at configuration time in the

initial block.  This means that when configuration completes, the state logic starts up immediately.

This is bad because the release of global set/reset is asynchronous to your clock.  If you have no

reset pin to the design, then a reset based on a shift register is OK.  This will delay startup for

a few clock cycles after configuration completes to ensure all of the logic starts up synchronously:

reg [3:0] rst_pipe = 4'hF;

reg local_reset = 1'b1;

always @ (posedge clk) {local_reset,rst_pipe} <= {rst_pipe,1'b0};

Then use local_reset to initialize the registers other than IMEM and MEM.

2) All of your state logic is in a clocked process, but all of the assignments are blocking.  This

is a recipe for mismatch between simulation and synthesis.  Using blocking assignments

inside a clocked process is allowed, but it is an advaced technique that requires a lot of

thought about how the signals are used.  I would suggest re-coding without the blocking

assignments, and getting rid of next_state.  i.e. instead of "next_state =decode;" write

"current_state <= decode;"

3) You say the output of the LED's is sporadic.  Is there any input to the design besides

the clock, and if not where does the clock come from?  Remember that using a push-button

as a clock requires debouncing.

-- Gabor

[skinwalker00]

Gabor,

Thanks for the information.

Point 1: This was great information. I think I understand what you mean about the need for the few clock cycle delay. However, I'm not sure what you mean by "use local_reset to initialize the registers". You wrote an always block "always @ (posedge clk) {local_reset,rst_pipe} <= {rst_pipe,1'b0};"  Am I supposed to initial in this block? This doesn't make sense as I don't want to initialize every positive clk edge.

Point 2: This makes total sense now. I didn't really understand blocking vs nonblocking. Due to your hint I looked up some information on this and now understand this.

Point 3: When I say sporadic, I mean that random LED's light up instead of the proper ones. You bring up a good point with debouncing. I'll try to figure out how to debounce in verilog. I'm guessing some sort of delay using a loop would be what I have to do.

Thanks for being patient with my newness to veilog.

Justin

[gszakacs · Accepted solution]

The idea of this reset:

reg [3:0] rst_pipe = 4'hF;

reg local_reset = 1'b1;

always @ (posedge clk) {local_reset,rst_pipe} <= {rst_pipe,1'b0};

is to give you a reset term to your clocked process like:

always @ (posedge clk or posedge local_reset) // Leave out "or local_reset" for synchronous reset

if (local_reset)

  begin

    bus <= 0;
    current_state <= 0;
    next_state <= 0;
    PC <= 0; // progam counter
    opcode <= 0;
    operand <= 0;

  end

else

  begin

    case(current_state)
      fetch: begin

    . . . .  More of your code

  end

This holds your regs in reset while local_reset is active.  It also means you

don't need to initialize the same registers in the initial block (but it doesn't hurt).

Note that I did not include MEM or IMEM in the top part of this process.  They

only get initialized in the initial block.

Regards,

Gabor

[skinwalker00]

Thanks so much for your help!!!!! It works now. Whoo hoo. I'm sure it's not the cleanest or best solution. I still need to master Verilog. I have attached my code in case anyone else wants to see how I did it.

Thanks again,

Justin