Synthesis

[johnaaa]

Hi All,

I'm using ISE Webpack 9.2i, getting to know it, and have purposely introduced errors so that I can see how the synthesis tool responds.  In particular I have mislabeled some internal nets in a small design, run the synthesis tool XST, and receive no errors or warnings in the console.  If I poke around I find several of the following messages under Detailed Reports->Synthesis Report.

WARNING:Xst:653 - Signal <n0> is used but never assigned. Tied to value 0.

What I would like for it to do is to take me to the line in my sources where the net is mislabeled.  Instead, if I click on the warning, it pops up a browser window with a generic explanation about the warning.

In a large design it would be most useful for the ISE to take me to the error so I can fix it.  Is there a way to navigate to the offending source line from the error/warning message?

Thanks in advance,

John

[briandrummond]

This is easy if you have explicitly named a signal n0.

But it looks like an intermediate signal generated by the synthesis process, so it could come from anywhere.

The most appropriate way to find the error is to simulate; and trace back from whichever output(s) are "XXXX".

[johnaaa]

Hi Brian, thanks for the reply.

Yes, it is an internal module net, placed there purposely by me (I know exactly where it is) so I could see how to debug this type of problem.  Unfortunately, simulation does not reveal any clues since the output from the module is reduced to a GND connection--see Xilinx AR#13959  http://www.xilinx.com/support/answers/13959.htm .  This is confirmed by the RTL schematic which shows the entire module replaced by a GND signal.

I ran the same test in ModelSimXE and got the same results--no error from compile, and the output signal from the module having value "X" for the entire simulation.

What bothers me about this is that I have undefined nets being used by AND and OR gates and yet neither the synthesis tool nor the simulators flag this as a problem.   At this point I need to figure out how to disable this "logic trimming" being done by ISE which in effect hides the problem.

I would expect this would be one of the first issues people face when using the ISE, i.e. trying to locate a typo in a net name, and would have expected the ISE to provide some kind of troubleshooting assistance.

John

[gszakacs · Accepted solution]

If you do a behavioral simulation, you should see undriven nets as U for VHDL or Z for Verilog.  Obviously

if you do post translate simulation you will see the signals driven low as indicated in the warning.

It is not easy for the synthesis to direct you to an error of this type, as the undriven net may just

indicate that you haven't finished the design that was intended to drive it, rather than a mis-

spelling.  In ISE your best friend for this sort of error is the design summary view which allows

you to filter out warnings that you usually ignore and see warnings of the type you want to know

about like undriven nets.

If the net was implicitly defined in Verilog, you can take advantage of the Verilog 2001 feature:

`default_nettype none

This will force an error when the implicit net is defined without a type (assuming the net is used.

Regards,

Gabor

[johnaaa]

Thanks Gabor,

This was _exactly_ what I needed.  I added the default_nettype directive, ran synthesis, and errors appeared with links that take me to the exact line in my source.  Fantastic!!!

I was not aware of this "implicit net declaration", however I plan to use "default_nettype none" in every source file.

Thanks again,

John