Synthesis

[tennirva]

       Hello, I'm having a problem in understanding the 2nd page of "Suggested Instantiation" in "Basic HDL Coding Techniques Training Video", maybe it's because of my point of view. As the video suggests that all instantiations (I think this means the "instantiations of FPGA resources", HDL-built modules can be instantiated too) should be in one place, I saw in the video that there are IOBUF, DCM, etc, these make sense to me that they appear at the top level. If so, how instantiations that works in different (lower) levels could be managed ? For example, an instantiated BRAM that I want to place in a deep submodule in my design.

       Sorry if I don't understand something correctly from the first place and if I'm not on the way on which the video is, I also posted my question on Youtube.

http://www.youtube.com/watch?v=EKCHww5kUok

Tennirva

[herver]

Hi Tennirva,

I think there is a little mis-interpretation;

The video tries to say that top level Xilinx specific blocks should be at the top level (or maybe one level down) but does not talk about BRAM in particular.

My take on the first few slides was that the IO blocks / DCM|PLL should be a the top and not burried deep down inside which will make the design hard to debug/port.

I watch only once, I may have missed something too :)

I hope this helps.

[bassman59]

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tennirva wrote:

       Hello, I'm having a problem in understanding the 2nd page of "Suggested Instantiation" in "Basic HDL Coding Techniques Training Video", maybe it's because of my point of view. As the video suggests that all instantiations (I think this means the "instantiations of FPGA resources", HDL-built modules can be instantiated too) should be in one place, I saw in the video that there are IOBUF, DCM, etc, these make sense to me that they appear at the top level. If so, how instantiations that works in different (lower) levels could be managed ? For example, an instantiated BRAM that I want to place in a deep submodule in my design.

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You can instantiate the Xilinx primitives wherever you want in your design hierarchy. There's no real reason to limit them to the top level of the design.

For example, I have a Camera Link transmitter module which instantiates OSERDES and the LVDS output buffers, and that entity is instantiated three times using a generate couple of levels down in the hierarchy. It would be madness to bring all of the control and data signals to the top level and back down to the lower level for handling.