Synthesis

[sraza]

Hello all

I am relatively new to FPGA designing

I have a querry that why do we need to check or uncheck the "write timing constrant" check box during systhesis setting.

I know it will write timing constraint in NGC file. But since we are giving timing constraints to the design using UCF file. So why need this.So either the UCF file will then be used in PAR or this. I am little confused in it.

If they are in collaboration what will be the hierarchy then.

Also will optimizing the speed increase my design size as I found no effect in the sumamry after changing the options.

Regards,

Shan

[bassman59]

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sraza wrote:

Hello all

I am relatively new to FPGA designing

I have a querry that why do we need to check or uncheck the "write timing constrant" check box during systhesis setting.

I know it will write timing constraint in NGC file. But since we are giving timing constraints to the design using UCF file. So why need this.So either the UCF file will then be used in PAR or this. I am little confused in it. If they are in collaboration what will be the hierarchy then.

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I don't bother with that feature. I just set my period and other implementation constraints in the UCF. 

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Also will optimizing the speed increase my design size as I found no effect in the sumamry after changing the options.

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Optimizing for speed might increase the design size, as the tools may replicate some logic. But depending on the required speed, such replication might not be necessary.

[viviany]

Timing constraints in UCF  has top priotity. So if you have conflicting timing constraint in NGC or UCF, the one in UCF will be used.

Usually if user chooses to "Write Timing Constraint" during Synthesis, he will not need to set the same Timing constraint in UCF any more.

Vivian