Hello,
I have a problem with unexpected ff trimming. The code below is a minaturized version that displays the problem (not 'real' code for my design).
The module has two 12-bit inputs One and Two which are each 'interpreted' as composed of 2 signals A and B 6 bits each which are 'unsigned'.
I take a difference diffOne of OneA and OneB and also diffTwo of TwoA and TwoB, then I take calculate squares of the differences and output the sum.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity demobug_top is
Port ( clk_in : in STD_LOGIC;
rst_in : in STD_LOGIC;
BigVarA: in std_logic_vector(11 downto 0);
BigVarB: in std_logic_vector(11 downto 0);
diffSq: out unsigned(12 downto 0));
end demobug_top;
architecture Behavioral of demobug_top is
signal VarOneA: unsigned(5 downto 0);
signal VarOneB: unsigned(5 downto 0);
signal VarTwoA: unsigned(5 downto 0);
signal VarTwoB: unsigned(5 downto 0);
signal VarOneA_reg : unsigned(5 downto 0);
signal VarOneB_reg : unsigned(5 downto 0);
signal VarTwoA_reg : unsigned(5 downto 0);
signal VarTwoB_reg : unsigned(5 downto 0);
signal diffOne_sig : unsigned(5 downto 0);
signal diffTwo_sig : unsigned(5 downto 0);
signal diffOne_reg : unsigned(5 downto 0);
signal diffTwo_reg : unsigned(5 downto 0);
signal diffOneSq_reg : unsigned(11 downto 0) := (others=>'0');
-- signal diffOneSq_reg : unsigned(11 downto 0);
signal diffTwoSq_reg : unsigned(11 downto 0) := (others=>'0');
-- signal diffTwoSq_reg : unsigned(11 downto 0);
signal diffSq_sig : unsigned(12 downto 0);
begin
VarOneA<=unsigned(BigVarA(11 downto 6));
VarTwoA<=unsigned(BigVarA(5 downto 0));
VarOneB<=unsigned(BigVarB(11 downto 6));
VarTwoB<=unsigned(BigVarB(5 downto 0));
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in='1' then
VarOneA_reg<=(others => '0');
VarOneB_reg<=(others => '0');
VarTwoA_reg<=(others => '0');
VarTwoB_reg<=(others => '0');
else
VarOneA_reg<=VarOneA;
VarOneB_reg<=VarOneB;
VarTwoA_reg<=VarTwoA;
VarTwoB_reg<=VarTwoB;
end if;
end if;
end process;
diffOne_sig<=VarOneB_reg-VarOneA_reg;
diffTwo_sig<=VarTwoB_reg-VarTwoA_reg;
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in='1' then
diffOne_reg<=(others => '0');
diffTwo_reg<=(others => '0');
else
diffOne_reg<=diffOne_sig;
diffTwo_reg<=diffTwo_sig;
end if;
end if;
end process;
process(clk_in)
begin
if rising_edge(clk_in) then
if rst_in='1' then
diffOneSq_reg<=(others => '0');
diffTwoSq_reg<=(others => '0');
else
diffOneSq_reg<=diffOne_reg*diffOne_reg;
diffTwoSq_reg<=diffTwo_reg*diffTwo_reg;
end if;
end if;
end process;
diffSq<=diffOneSq_reg+('0'&(diffTwoSq_reg));
end Behavioral;
Synthesis displays a warning and an info message that I find worrying:
Xst:1710 - FF/Latch <Maddsub_diffOne_reg[5]_diffOne_reg[5]_MuLt_18_OUT_12> (without init value) has a constant value of 0 in block <demobug_top>. This FF/Latch will be trimmed during the optimization process.
Xst:2677 - Node <Maddsub_diffOne_reg[5]_diffOne_reg[5]_MuLt_18_OUT_1> of sequential type is unconnected in block <demobug_top>.
Xst:2677 - Node <Maddsub_diffOne_reg[5]_diffOne_reg[5]_MuLt_18_OUT_0> of sequential type is unconnected in block <demobug_top>.
Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_diffTwo_reg[5]_diffTwo_reg[5]_MuLt_19_OUT by adding 1 register level(s).
The question is - why does the synthesis flag this - I think the values in the register should not in general be constant...
Why does this happen? Why only the FF for One is trimmed and not the FF for Two ?
The latter two warnings are most likely the result of the first one.
Ant then the second question - about the Xst:2385 - why does this happen. I thought I already did the right thing with putting a sync reset register so that the FF inside the DSP48E1 would be used. In fact the snip from the console seems to say that but still I get this message - why?
Here is the XST console snip:
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Synthesizing (advanced) Unit <demobug_top>.
Multiplier <Mmult_diffOne_reg[5]_diffOne_reg[5]_MuLt_18_OUT> in block <demobug_top> and adder/subtractor <Madd_diffSq> in block <demobug_top> are combined into a MAC<Maddsub_diffOne_reg[5]_diffOne_reg[5]_MuLt_18_OUT>.
The following registers are also absorbed by the MAC: <diffOneSq_reg> in block <demobug_top>.
Found pipelined multiplier on signal <diffTwo_reg[5]_diffTwo_reg[5]_MuLt_19_OUT>:
- 1 pipeline level(s) found in a register connected to the multiplier macro output.
Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_diffTwo_reg[5]_diffTwo_reg[5]_MuLt_19_OUT by adding 1 register level(s).
Unit <demobug_top> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# MACs : 1
6x6-to-13-bit MAC : 1
# Multipliers : 1
6x6-bit registered multiplier : 1
# Adders/Subtractors : 2
6-bit subtractor : 2
# Registers : 36
Flip-Flops : 36
In fact why only one registered 6x6 multiplier is infered?
I am working with Virtex 6 (hc6vhx565t-1ff1924).
Thank you for your help,
Wojtek
