Synthesis

[jaredcasper]

Just got bit by what appears to be a problem with XST and the $clog2 verilog function.

Using XST 11.3 and the simple testbench

module tb;
parameter A = $clog2(325);
endmodule

I get:

 =========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <tb>.
    Related source file is "/home/jcasper/tmp/vtmp/clog2.v".
        A = 6
    Summary:
        no macro.
Unit <tb> synthesized.

I would expect A to be 9, the ceiling of log2(325), not 6, which seems to come out of left field.  Am I confused or does XST not know how to calculate clog2?

[jaredcasper]

Playing around with more numbers and it appears to be calculating the ceiling of the natural log, not log base 2.  So I guess the numbers aren't coming out of left field, but still just plain wrong.

[austin]

jc,

I can't find any support for that function in the xst manual.

In fact, I can't find any support for that function in vhdl.

The standard does not define arithmetic functions (beyond the simplest) so that will be dependent on the library that you are including for math functions.

Whose library are you including?

[jaredcasper]

$clog2 was added to the verilog standard in IEEE 1364-2005 (section 17.11.1).  I assumed since there was no errors or warnings that XST had implemented it (or at least tried to).  I'm not explicitely including any math libraries, so I guess it is just using whatever is default.  The clog2.v file which just contains the three-line module listed is the only file given to XST.

[jaredcasper]

Just to be clear:

 $ cat clog2.v
module tb;
parameter A = $clog2(325);
endmodule

$ cat clog2.prj
verilog work clog2.v

$ cat clog2.scr
run
-p xc6slx16-2-csg324
-top tb
-ifn clog2.prj
-ofn clog2.ngc

$ xst -ifn clog2.scr -intstyle ise

....

 Synthesizing Unit <tb>.
    Related source file is "/home/jcasper/tmp/vtmp/clog2.v".
        A = 6   

    Summary:
        no macro.
Unit <tb> synthesized.

[sandbender]

XST does not support $clog2 since it is a Verilog 2005 construct. However, you can write your own version of the function. You can use it as a constant function when you compute port widths and so forth. There is a catch though. XST has a bug where it can't use constant functions anywhere except the right hand side of parameter assignments. So, you need to have a parameter declared as the result of the constant function and then use the parameter in your port declarations.

You can read a detailed description of this on my blog...

http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/

-Pete 

[jaredcasper]

Well if it doesn't support it, it should issue an error and not attempt to support it incorrectly.

Thanks for the tip about the constant function issues.

[woutersj]

Hi,

We defined this as a Verilog macro and that works fine on most tools. Curiously, the same tools seem to have little difficulty understanding it on VHDL as a function. If you'd like to see the verilog, please tell me.

Johan

[nicetyproject]

Well, this is weird. Having log10 result from log2 name function with no sign of warning or error...

Here's a workaround if someone will prefer to use 'officially not supported' built-in functions over constant-functions approach:

module counter #(
  parameter COUNTER_VALUE = 17,
  parameter integer COUNTER_WIDTH = $ceil($log10(COUNTER_VALUE)/$log10(2))
) ...

the important part is to force type of COUNTER_WIDTH to integer (otherwise it's 'real' and no chance to specify a range with it). Expression inside $ceil() call is just a use of one of math properties of log functions: log2(x) = log10(x)/log10(2). Seems to work for 13.1 although it's not documented...

Regards,

Vladislav