According to David Bishop in Xilinx forum: http://forums.xilinx.com/t5/Simulation-and-Verification/VHDL-fixed-point-package-support-in-ISE-simu..., the fixed_pkg_c package shoud work in ISE and while Xilinx ISE not support VHDL2008, this package is the only solution for using fixed numbers.
I followed his advises to his packages VS ISE:
Things Xilinx m11.1i didn't like about these packages:
1) 'instance_name showed as a syntax error, replace with package name
2) "to_stdlogicvector(to_sulv(arg))" shows as a type conversion error, replace
with casting "std_logic_vector(arg)"
3) Did not like any of the fixed point division routines,
had to comment them out.
4) Had to comment out the "?=" routines, XST could not deal with that syntax.
Now i reduced the amount of syntax errors greatly, but i still getting error because of this lines in the end of the package file:
-- pragma synthesis_on
-- rtl_synthesis on
-- IN VHDL-2006 std_logic_vector is a subtype of std_ulogic_vector, so these
-- extra functions are needed for compatability.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_ufixed) -- for size only
return UNRESOLVED_ufixed is
begin
return to_ufixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : UNRESOLVED_sfixed) -- for size only
return UNRESOLVED_sfixed is
begin
return to_sfixed (
arg => to_stdulogicvector (arg),
size_res => size_res);
end function to_sfixed;
-- unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_ufixed is
begin
return to_UFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return UNRESOLVED_sfixed is
begin
return to_SFix (
arg => to_stdulogicvector (arg),
width => width,
fraction => fraction);
end function to_SFix;
I'm out of solutions, so if somebody is able to use fixed numbers in ISE, please write it down how to...
