02-27-2012 07:19 AM - edited 02-27-2012 07:20 AM
I'm trying to implement distributed dual clock RAM but the XST implements it as block RAM. I'm using the recommended coding styles for RAM implementation in the xst user guide. I tried the attribute distributed_ram but it did not work.
process(wrclk,rstn) begin if rstn='0' then aRAM <= (others=>(others=>'0')); ElsIf rising_edge(wrclk) then if wrreq='1' then aRAM(conv_integer(wr_Address)) <= wr_data; end if; end if; end process; process(rdclk,rstn) begin if rstn='0' then rd_data <= (others=>'0'); Elsif rising_edge(rdclk) then if rdreq='1' then rd_data <= aRAM(conv_integer(rd_address)); end if; end if; end process;
Another question : If i implemented a dual clock RAM with data width equal 1 bit with with 16 memory locations so, Am I in this case missusing the block RAM resources ? Should be there a minimum data width of the Block RAM ?
Thanks in advance.
Solved! Go to Solution.
02-27-2012 11:46 PM
May be you did not understand my problem. I need to implement this code as DISTRIBUTED ram but the XST implements it as BLOCK ram. I added the reset to prevent the XST from implementing the code as BLOCK ram.
02-28-2012 01:19 AM
Are you referring to "ram_style" attribute when you say "attribute distributed_ram"? How do you add this attribute in your code? I suspect you used incorrect attribute so XST does not infer the RAM as you expected.
02-28-2012 03:41 AM
attribute syn_ramstyle : string; attribute syn_ramstyle of aRAM : signal is "distributed_ram";
May be there is a problem with the attribute. Check my code above and correct me.