Synthesis

[josephnguyen]

I would like to use the generate function to generate three case statements.  However, I keep getting this error:

ERROR:HDLParsers:839 - "C:/Xilinx_VHDL/SS-MUX/117082/117082.vhd" Line 764. Selector (Slice name of type std_logic_vector) is an unconstrained array.

generate_portmode: for i in 0 to 2 generate
begin

case portmode((i*8)+7 downto (i*8)+4) is  -- this is what the compiler doesn't like

--case portmode(7 downto 4) is  -- this works, but then I would have to write three separate, really long case statements

--case portmode(15 downto 12) is

--case portmode(23 downto 20) is

[l889]

I experienced the same and imho there is no solution for generationg case... Try using to generate the same functionality with the IF statement in a process...

regards, JJ

[bassman59]

---

josephnguyen wrote:

I would like to use the generate function to generate three case statements.  However, I keep getting this error:

ERROR:HDLParsers:839 - "C:/Xilinx_VHDL/SS-MUX/117082/117082.vhd" Line 764. Selector (Slice name of type std_logic_vector) is an unconstrained array.

generate_portmode: for i in 0 to 2 generate
begin

case portmode((i*8)+7 downto (i*8)+4) is  -- this is what the compiler doesn't like

--case portmode(7 downto 4) is  -- this works, but then I would have to write three separate, really long case statements

--case portmode(15 downto 12) is

--case portmode(23 downto 20) is

---

Case statements need to be in processes.

-a

[josephnguyen]

bassman59 - yes, i know they need to be in a process, i was just abbreviating the code so the msg wouldn't be too long and i didn't want to confuse anyone.  although i probably caused more confusion by abbreviating.  thanks for your reply.

-- this is what the compiler doesn't like 

generate_portmode: for i in 0 to 2 generate
begin

case portmode((i*8)+7 downto (i*8)+4) is

-----------------------------------------------------------

-- this works, but then I would have to write three separate, really long case statements

case portmode(7 downto 4) is

case portmode(15 downto 12) is

case portmode(23 downto 20) is

[gamomchristian]

Hi,

here is the code i want to compile but the use of an index is not accepted

Can you help me to correct this issue ?

Thanks

switch16x16 : if number_of_ports = 16 generate
switch_16x16 :for i in 1 to number_of_ports generate
begin
j<=number_of_ports*(i-1);
PORTx16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
GENERIC MAP(number_of_ports =>16)
PORT MAP(
data_in => Port_in(i),
data_in_en => data_in_en(i),
reset => reset,
clk =>clk,
grant(j+1) => grant_signal(j+1),
grant(j+2) => grant_signal(j+2),
grant(j+3) => grant_signal(j+3),
grant(j+4) => grant_signal(j+4),
grant(j+5) => grant_signal(j+5),
grant(j+6) => grant_signal(j+6),
grant(j+7) => grant_signal(j+7),
grant(j+8) => grant_signal(j+8),
grant(j+9) => grant_signal(j+9),
grant(j+10) => grant_signal(j+10),
grant(j+11) => grant_signal(j+11),
grant(j+12) => grant_signal(j+12),
grant(j+13) => grant_signal(j+13),
grant(j+14) => grant_signal(j+14),
grant(j+15) => grant_signal(j+15),
grant(j+16) => grant_signal(j+16),
fifo_full =>fifo_in_full(i),
priority_rotation => priority_rotation_signal(i),
fifo_empty => fifo_in_empty(i),
data_out =>crossbar_in_port(i),
data_out_pulse =>crossbar_in_pulse(i),
request(j+1) =>request_signal(j+1),
request(j+2) =>request_signal(j+2),
request(j+3) =>request_signal(j+3),
request(j+4) =>request_signal(j+4),
request(j+5) =>request_signal(j+5),
request(j+6) =>request_signal(j+6),
request(j+7) =>request_signal(j+7),
request(j+8) =>request_signal(j+8),
request(j+9) =>request_signal(j+9),
request(j+10) =>request_signal(j+10),
request(j+11) =>request_signal(j+11),
request(j+12) =>request_signal(j+12),
request(j+13) =>request_signal(j+13),
request(j+14) =>request_signal(j+14),
request(j+15) =>request_signal(j+15),
request(j+16) =>request_signal(j+16)
);
end generate switch_16x16;
end generate switch16x16;

[eteam00]

g,

I noticed you started a fresh thread for your topic.  Thank you for doing this.

-- Bob Elkind