driesd wrote:
running a simulation should also reveal why only 1 of the 64-bits is used.
Actually I ran a simulation as shown in the pdf you linked in your previous post. In the simulation it seems that no output is affected by the incoming signals. It may mean that my coding is uncorrect but I also implemented a dual port ram as shown in VHDL Coding Examples from the software manuals and even in that case no output is affected. What could be the reason?
I modeled the waveforms without payng too much attention to their reliability: can it possibly be the cause of it all?
Also I wonder how can I synthetize a block as top-level.
At any rate it stopped giving me warning messages when I completed the else branches with null statements as follows:
entity read_RAM is
Generic ( ADDR : integer := 5;
WIDTH : integer := 13;
DEPTH : integer := 63
);
Port ( stateArray : in STD_LOGIC_VECTOR (DEPTH downto 0);
clk : std_logic;
enable : in STD_LOGIC; -- rd or dl
-- rdX : out STD_LOGIC; -- rd1 or rd2
aX : out STD_LOGIC_VECTOR (ADDR downto 0)); -- a1 or a2
end read_RAM;
architecture Behavioral of read_RAM is
-- signal read_enable : std_logic;
begin
process(clk, enable)
begin
if (rising_edge(clk)) then
if enable = '1' then
for i in DEPTH downto 0 loop
if stateArray(i) = '1' then
-- read_enable <= '1';
aX <= std_logic_vector(conv_unsigned(i, 6));
else
-- read_enable <= not(read_enable);
null;
end if;
end loop;
else
-- read_enable <= not(read_enable);
null;
end if;
end if;
end process;
-- rdX <= read_enable;
end Behavioral;
This doesn't make sense to me, but it works.
Message Edited by xinuver on 12-22-2008 11:30 PM
