Synthesis

[ruwan1988]

we needed to duplicate the code "rel.v"(attached below).so the approach followed was creating a top layer as in the "rel1.v"

but in the synthesis report & routing  there is no change visible. is it due to optimiziing of the tool?? or coding error?? please help...

also need to know about syntax of "dont_touch" in verilog..

[bhayes47]

Hi ruwan1988,

You have reversed the correct order of the generic module name and the specific instantiation name.

In verilog, the generic name comes first, then the instantiation name, eg.,

    rel  #(.N(N))  rel1_A(

Bill

[bhayes47]

Hi ruwan1988,

After having some coffee, I just noticed that, in addition to the incorrect instantiation order I mentioned before, you also used the same name for both modules, the top level and the instantiated level.

I assume you aren't trying to do recursive instantiation, and if you are, I don't think the way you've done it would work.

Try changing the top level module name to something else like rel_array.

Bill

[ruwan1988]

thanx bhayes47,,

actually we are  trying to duplicate our code as a reliability improvement process,, nw  the duplication part is ok, bt nw i hv to design the automatic controller for the mux  which is monitoring the process of each instance...hw can i  do that?? the purpose of this is to identify a failure  of fpga and rout the circuit for another instance.. thnx again ...cheers!!!

[bhayes47]

Hi ruwan1988,

I'm not sure if when you use the word "design",  do you mean "design", or "implement".

By "design", I mean study and understand the problem to be solved, and devise a structure and/or algorithm to

solve it.

By "implement", I mean that, having a design in mind, you seek to write HDL to create the structure and/or algorithm

in a way that:

1) logically works

2) is intelligable to yourself and others

3) meets timing

4) uses a reasonable amount of resources

In either case, your question is too vague for me to give a meaningful answer.

I can't, and won't, "design" it for you, first off, because I don't understand what you're trying to acheive.

What do you mean by "failure of fpga" ?

If you have a more specific implementation issue you need help with, and you can  describe it more

clearly, perhaps I or others can assist you.

Bill

[ruwan1988]

hi bhayes47,

actually i'm trying to implement electronic redundancy circuit inside fpga, as a reliability improvement method.

if one instance failes due to failure (in a routing path ,CLB etc..) the contoller should identify it and and transfer the circuit to the duplicated one and generate a warning message....

can u tell me a method to "implement" this idea...

thanx...

[bhayes47]

Hi ruwan1988,

I have no experience with TMR, and as rcingham said, doing this properly may be difficult,

and of course the difficulty of the solution is dependent on how critical is the resultant behavior.

So, with those caveats, a simple solution may be to just have a selector that picks one of the machines

as the master, and continually compares the output (or state) of the selected master with the other two non-masters.

If the master output disagrees with both of the other two, and we assume a single fault (only one machine will fault at any one time), then implicitly the other two agree, and we should switch to either of them as the new master.

So that is my basic design statement.   It may or may not be a good design, as I said, I have no experience with TMR.

To implement that design idea, I envision a shift register as my master selection pointer, a mux to select one machine output as the master output, a fault detect signal that compares the current master output with each of the other two outputs. When a fault is detected, the current master outputs will be momentarily blocked from the output until the shift register is shifted to a new master, and an output pulse is generated to signal that a fault has occurred.

There are a variety of ways you could implement a given design idea, and a variety of ways to code a specific implementation approach.

Attached is an example of one way you could code this implementation.

Your design requirements description was still a little thin, so I'm not

sure if my description is off base or on target.

Good luck,

Bill

[ruwan1988]

thanx bhayes47,,

thats exactly what i want,and  next is the main problem,,,,how to validate this implementation ??,, is there any method to  generate error in one instance???