Synthesis

[deepak.goyal]

I am using HDL designer with xilinx ise for synthesis.

I am getting similar warning for all components of unisim library.

How to make definitions of these component available to synthesis tool?

[viviany]

How do you instantiate the ibuf primitive in your code?

These primitives do be available to Synthesis tool, although you receive these warnings. These warnings does not negatively affect the Synthesis process but if you want to remove these warnings, you may need to change the way you instantiate the primitives.

Vivian

[deepak.goyal]

--library declaration

library unisim;

-- synopsys translate_off

for all : IBUF use entity unisim.IBUF;

-- synopsys translate_on

--ibuf declaration

I0 : IBUF generic map ( CAPACITANCE => "DONT_CARE", IBUF_DELAY_VALUE => "0", IBUF_LOW_PWR => TRUE, IFD_DELAY_VALUE => "AUTO", IOSTANDARD => "DEFAULT" ) port map ( O => Mezz_TDO_i, I => Mezz_TDO );

[mcgett]

You forgot.

use unisim.vcomponents.all;