I am writing a verilog code which runs ok and gives correct output but is not synthesizable i.e. it gives error "signal is connected to multiple drivers". I don't know where is am making mistake. Kindly help me out as early as possible. I am here pasting my code here.
module MixColumn2 (input [127:0] state, input clk, input rst, output reg [127:0] MixColumnState,output reg signal);
reg [31 : 0] col1, col2, col3, col4;
reg [31 : 0] col1_saveVal, col2_saveVal, col3_saveVal, col4_saveVal;
reg [31 : 0] col1_shifted, col2_shifted, col3_shifted, col4_shifted;
integer xor_val_col1, xor_val_col2, xor_val_col3, xor_val_col4;
reg [7:0] cycle_count;
reg [7:0]MSB_Save_1,MSB_Save_2,MSB_Save_3,MSB_Save_4;
always @ (clk)
if (!rst)
begin
col1 <= 0;
col2 <= 0;
col3 <= 0;
col4 <= 0;
cycle_count <= 0;
col1_saveVal <= 0;
col2_saveVal <= 0;
col3_saveVal <= 0;
col4_saveVal <= 0;
col1_shifted <= 0;
col2_shifted <= 0;
col3_shifted <= 0;
col4_shifted <= 0;
xor_val_col1 = 0;
xor_val_col2 = 0;
xor_val_col3 = 0;
xor_val_col4 = 0;
MixColumnState <= 0;
cycle_count <= 0;
signal <= 0;
end
else
begin
if (cycle_count == 0)
begin
col1 <= {state [127:120], state [95:88], state [63:56], state [31:24]} ;
col2 <= {state [119:112], state [87:80], state[55:48], state [23:16]};
col3 <= {state[111:104], state [79:72], state [47:40], state [15:8]};
col4 <= {state [103:96], state [71:64], state [39:32], state [7:0]};
end
else if(cycle_count == 5)
begin
MixColumnState[127:96] <= {col1_shifted [31 : 24],col2_shifted [31 : 24],col3_shifted [31 : 24],col4_shifted [31 : 24]} ;
MixColumnState[95:64] <= {col1_shifted [23 : 16],col2_shifted [23 : 16],col3_shifted [23 : 16],col4_shifted [23 : 16]} ;
MixColumnState[63:32] <= {col1_shifted [15 : 8],col2_shifted [15 : 8],col3_shifted [15 : 8],col4_shifted [15 : 8]} ;
MixColumnState[31:0] <= {col1_shifted [7 : 0],col2_shifted [7 : 0],col3_shifted [7 : 0],col4_shifted [7 : 0]} ;
signal <= 1;
end
else
begin
col1 <= col1 << 8;
col2 <= col2 << 8;
col3 <= col3 << 8;
col4 <= col4 << 8;
// Shifting values for adding next time
col1_shifted [31 : 24] <= col1_saveVal [23 : 16];
col1_shifted [23 : 16] <= col1_saveVal [15 : 8];
col1_shifted [15 : 8] <= col1_saveVal [7 : 0];
col1_shifted [7 : 0] <= col1_saveVal [31 : 24];
col2_shifted [31 : 24] <= col2_saveVal [23 : 16];
col2_shifted [23 : 16] <= col2_saveVal [15 : 8];
col2_shifted [15 : 8] <= col2_saveVal [7 : 0];
col2_shifted [7 : 0] <= col2_saveVal [31 : 24];
col3_shifted [31 : 24] <= col3_saveVal [23 : 16];
col3_shifted [23 : 16] <= col3_saveVal [15 : 8];
col3_shifted [15 : 8] <= col3_saveVal [7 : 0];
col3_shifted [7 : 0] <= col3_saveVal [31 : 24];
col4_shifted [31 : 24] <= col4_saveVal [23 : 16];
col4_shifted [23 : 16] <= col4_saveVal [15 : 8];
col4_shifted [15 : 8] <= col4_saveVal [7 : 0];
col4_shifted [7 : 0] <= col4_saveVal [31 : 24];
end
cycle_count <= cycle_count + 1;
end
always @(xor_val_col1, xor_val_col2, xor_val_col2, col1_shifted, col2_shifted, col3_shifted, col4_shifted )
begin
xor_val_col1 = 0;
xor_val_col2 = 0;
xor_val_col3 = 0;
xor_val_col4 = 0;
if (col1 [31] == 1)
xor_val_col1 = 8'b 00011011;
if (col2 [31] == 1)
xor_val_col2 = 8'b 00011011;
if (col3 [31] == 1)
xor_val_col3 = 8'b 00011011;
if (col4 [31] == 1)
xor_val_col4 = 8'b 00011011;
// main processing
MSB_Save_1 = (col1 [31 : 24] * 2) ^ xor_val_col1;
col1_saveVal [31:24] = MSB_Save_1 ^ col1_shifted [31:24]; // 02
col1_saveVal [23:16] = col1 [31 : 24] ^ col1_shifted [23 : 16]; // 01
col1_saveVal [15:8] = col1 [31 : 24] ^ col1_shifted [15 : 8]; // 01
col1_saveVal [7:0] = MSB_Save_1 ^ col1 [31:24] ^ col1_shifted [7 : 0]; //03 b1 xor bf xor b3
MSB_Save_2 = (col2 [31 : 24] * 2) ^ xor_val_col2;
col2_saveVal [31:24] = MSB_Save_2 ^ col2_shifted [31:24];
col2_saveVal [23:16] = col2 [31 : 24] ^ col2_shifted [23 : 16];
col2_saveVal [15:8] = col2 [31 : 24] ^ col2_shifted [15 : 8];
col2_saveVal [7:0] = MSB_Save_2 ^ col2 [31:24]^ col2_shifted [7 : 0];
MSB_Save_3 = (col3 [31 : 24] * 2) ^ xor_val_col3 ;
col3_saveVal [31:24] = MSB_Save_3 ^ col3_shifted [31:24];
col3_saveVal [23:16] = col3 [31 : 24] ^ col3_shifted [23 : 16];
col3_saveVal [15:8] = col3 [31 : 24] ^ col3_shifted [15 : 8];
col3_saveVal [7:0] = MSB_Save_3 ^ col3 [31:24]^ col3_shifted [7 : 0];
MSB_Save_4 = (col4 [31 : 24] * 2) ^ xor_val_col4;
col4_saveVal [31:24] = MSB_Save_4 ^ col4_shifted [31:24];
col4_saveVal [23:16] = col4 [31 : 24] ^ col4_shifted [23 : 16];
col4_saveVal [15:8] = col4 [31 : 24] ^ col4_shifted [15 : 8];
col4_saveVal [7:0] = MSB_Save_4 ^ col4 [31:24] ^ col4_shifted [7 : 0];
end
endmodule
The error shows...
ERROR:Xst:528 - Multi-source in Unit <MixColumn2> on signal <col4_saveVal<26>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <MixColumn2> on signal <col4_saveVal<25>>; this signal is connected to multiple drivers.
ERROR:Xst:528 - Multi-source in Unit <MixColumn2> on signal <col4_saveVal<24>>; this signal is connected to multiple drivers.
In this way for all the indexes of col1_saveVal, col2_saveVal, col3_saveVal, col4_saveVal. Waiting for your quick response.
