09-09-2010 11:05 PM - edited 09-09-2010 11:06 PM
Solved! Go to Solution.
09-09-2010 11:59 PM
"port > of logic node" sounds strange, but "has no source" means that there is no assignment for that port, and so it probably will be optimized away.
Do you ave any idea what port in which module is referenced to by the error message?
Have a nice synthesis
10-13-2011 09:49 AM
the code has no syntax error output also coming while simulation.i am getting this error while synthesising
"ERROR:Xst:1706 - Unit <fft_8_image>: port <rr_17_index0001> of logic node <ri_19_mux0000<1>>
10-13-2011 06:54 PM
Hi Balajitiger, please create a new post for your question. This thread is closed. Thanks.
Post your code in your message as well so that others can advise why this error is given.