Synthesis

[hemapriya23]

Xst:1706 - Unit : port > of logic node has no source i have this error in synthesis...i check all sources....anybody face this problem?

[eilert]

Hi,

"port > of logic node"  sounds strange, but "has no source" means that there is no assignment for that port, and so it probably will be optimized away.

Do you ave any idea what port in which module is referenced to by the error message?

Have a nice synthesis

  Eilert

[driesd]

Hi Hempriya,

if you're not able to solve it, I would recommend posting your source code so we can give advice.

Best regards,

Dries

[hemapriya23 · Accepted solution]

hi...i rectify that...i have done mistake in signal declaration.nw its synthesized successfully

[balajitiger]

the code has no syntax error output also coming while simulation.i am getting this error while synthesising

"ERROR:Xst:1706 - Unit <fft_8_image>: port <rr_17_index0001> of logic node <ri_19_mux0000<1>> 

[viviany]

Hi Balajitiger, please create a new post for your question. This thread is closed. Thanks.

Post your code in your message as well so that others can advise why this error is given.

Vivian