When i used complex data types in my VHDL code , i can simulate using modelsim XE6.3c but i couldnt synthesize the code in xilinx. When i synthesize using xilinx 9.2i, it showing error as "data type: complex can not be supported in lite version"... pls can any one suggest me how to syntesize my code?? what should i do for syntesising the complex data type????
