warning saying a port is never used

juansiahaan · ‎04-16-2012

Hi everyone,

I'm trying to make a test code of a receiver block (not fully complete yet). I tried to synthesize it to check the warnings. I found out that the XST said that there's an input port that is never used. This caused a further warning saying that my output port (which is drive by my input port) to be constantly 0. Can anyonye help me to find the solution and explain why? I'll provide you my code.

dsb : process (CLK, RST, Frame, SDI0, SDI1, SDI2, SDI3, SDI4, SDI5, SDI6, SDI7)
	variable count : natural range 0 to 11 := 0;
	variable listen_time : natural range 0 to 274 := 0;
	begin
		if rising_edge (CLK) then
		framex <= Frame;
			if RST = '1' then
				count := 0;
				New_data <= '0';
				buffer0 <= (others => '0');
				buffer1 <= (others => '0');
				buffer2 <= (others => '0');
				buffer3 <= (others => '0');
				buffer4 <= (others => '0');
				buffer5 <= (others => '0');
				buffer6 <= (others => '0');
				buffer7 <= (others => '0');		
			else
				case s is
					when s0 =>
						if (trigger0 = '1') then
							if listen_time <= 275 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 275 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
							elsif listen_time = 275 then
								CE <= '1';
								if (framex = '0' and Frame = '1') then -- this is the proble
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s1;
									else
										count := count + 1;
									end if;
								end if;
							end if;
						end if;
					when others =>
						s <= s0;
				end case;
			end if;	
		end if;
	end process dsb;


end Behavioral;

Thanks in advance.

Regards,

Juan

juansiahaan · ‎04-16-2012

I re-synthesized the code again and the design summary said that I've used more than available bonded IOBs....does anyone know why? How can I reduce the IOBs?

juansiahaan · ‎04-16-2012

Now I'm having 537 warnings...the warning types are in the attachment and below is my most recent code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test_src is
	PORT (CLK : in std_logic;
			RST : in std_logic;
			SDI0 : in std_logic;
			SDI1 : in std_logic;
			SDI2 : in std_logic;
			SDI3 : in std_logic;
			SDI4 : in std_logic;
			SDI5 : in std_logic;
			SDI6 : in std_logic;
			SDI7 : in std_logic;
			Frame : in std_logic;
			Q0 : out std_logic_vector (31 downto 0) := (others => '0');
			Q1 : out std_logic_vector (31 downto 0) := (others => '0');
			Q2 : out std_logic_vector (31 downto 0) := (others => '0');
			Q3 : out std_logic_vector (31 downto 0) := (others => '0');
			Q4 : out std_logic_vector (31 downto 0) := (others => '0');
			Q5 : out std_logic_vector (31 downto 0) := (others => '0');
			Q6 : out std_logic_vector (31 downto 0) := (others => '0');
			Q7 : out std_logic_vector (31 downto 0) := (others => '0');
			CE : out std_logic := '0';
			New_data : out std_logic := '0'
			);
end test_src;

architecture Behavioral of test_src is

--Peak detector block
COMPONENT peak_detector_src
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		SDI0 : IN std_logic;
		SDI1 : IN std_logic;
		SDI2 : IN std_logic;
		SDI3 : IN std_logic;
		SDI4 : IN std_logic;
		SDI5 : IN std_logic;
		SDI6 : IN std_logic;
		SDI7 : IN std_logic;
		PEAK0 : OUT std_logic;
		PEAK1 : OUT std_logic;
		PEAK2 : OUT std_logic;
		PEAK3 : OUT std_logic;
		PEAK4 : OUT std_logic;
		PEAK5 : OUT std_logic;
		PEAK6 : OUT std_logic;
		PEAK7 : OUT std_logic
		);
	END COMPONENT;

--signals for test
signal framex : std_logic; -- for Frame
signal buffer0 : std_logic_vector (31 downto 0); --buffers from SDI0 until SDI7
signal buffer1 : std_logic_vector (31 downto 0);
signal buffer2 : std_logic_vector (31 downto 0);
signal buffer3 : std_logic_vector (31 downto 0);
signal buffer4 : std_logic_vector (31 downto 0);
signal buffer5 : std_logic_vector (31 downto 0);
signal buffer6 : std_logic_vector (31 downto 0);
signal buffer7 : std_logic_vector (31 downto 0);
signal trigger0 : std_logic;-- declaration for peak detection block
signal trigger1 : std_logic;
signal trigger2 : std_logic;
signal trigger3 : std_logic;
signal trigger4 : std_logic;
signal trigger5 : std_logic;
signal trigger6 : std_logic;
signal trigger7 : std_logic;

-- for case statement
type state is (s0, s1, s2, s3, s4, s5, s6, s7);
signal s : state := s0;

begin

Inst_peak_detector_src: peak_detector_src PORT MAP(
		CLK => CLK,
		RST => RST,
		SDI0 => SDI0,
		SDI1 => SDI1,
		SDI2 => SDI2,
		SDI3 => SDI3,
		SDI4 => SDI4,
		SDI5 => SDI5,
		SDI6 => SDI6,
		SDI7 => SDI7,
		PEAK0 => trigger0,
		PEAK1 => trigger1,
		PEAK2 => trigger2,
		PEAK3 => trigger3,
		PEAK4 => trigger4,
		PEAK5 => trigger5,
		PEAK6 => trigger6,
		PEAK7 => trigger7
	);

	--main process
	test : process (CLK, RST, Frame, SDI0, SDI1, SDI2, SDI3, SDI4, SDI5, SDI6, SDI7)
	variable count : natural range 0 to 11 := 0;
	variable listen_time : natural range 0 to 274 := 0;
	begin
		if rising_edge (CLK) then
		framex <= Frame;
			if RST = '1' then
				count := 0;
				listen_time := 0;
				New_data <= '0';
				buffer0 <= (others => '0');
				buffer1 <= (others => '0');
				buffer2 <= (others => '0');
				buffer3 <= (others => '0');
				buffer4 <= (others => '0');
				buffer5 <= (others => '0');
				buffer6 <= (others => '0');
				buffer7 <= (others => '0');		
			else
				case s is
					when s0 =>
						if (trigger0 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								listen_time := 0;
								CE <= '1';
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s1;
									else
										count := count + 1;
										s <= s0;						
									end if;
								end if;
							end if;
						end if;
					when s1 =>
						if (trigger1 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s2;
									else
										count := count + 1;
										s <= s1;						
									end if;
								end if;
							end if;
						end if;
					when s2 =>
						if (trigger2 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s3;
									else
										count := count + 1;
										s <= s2;						
									end if;
								end if;
							end if;
						end if;
					when s3 =>
						if (trigger3 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s4;
									else
										count := count + 1;
										s <= s3;						
									end if;
								end if;
							end if;
						end if;
					when s4 =>
						if (trigger4 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
									listen_time := 0;
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s5;
									else
										count := count + 1;
										s <= s0;						
									end if;
								end if;
							end if;
						end if;
					when s5 =>
						if (trigger5 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s6;
									else
										count := count + 1;
										s <= s5;						
									end if;
								end if;
							end if;
						end if;
					when s6 =>
						if (trigger6 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s7;
									else
										count := count + 1;
										s <= s6;						
									end if;
								end if;
							end if;
						end if;
					when s7 =>
						if (trigger7 = '1') then
							if listen_time <= 274 then
								buffer0 <= buffer0 (30 downto 0) & SDI0;
								buffer1 <= buffer1 (30 downto 0) & SDI1;
								buffer2 <= buffer2 (30 downto 0) & SDI2;
								buffer3 <= buffer3 (30 downto 0) & SDI3;
								buffer4 <= buffer4 (30 downto 0) & SDI4;
								buffer5 <= buffer5 (30 downto 0) & SDI5;
								buffer6 <= buffer6 (30 downto 0) & SDI6;
								buffer7 <= buffer7 (30 downto 0) & SDI7;
								listen_time := listen_time + 1;
							elsif listen_time > 274 then
								buffer0 <= (others => '0');
								buffer1 <= (others => '0');
								buffer2 <= (others => '0');
								buffer3 <= (others => '0');
								buffer4 <= (others => '0');
								buffer5 <= (others => '0');
								buffer6 <= (others => '0');
								buffer7 <= (others => '0');
								listen_time := 0;
							elsif listen_time = 274 then
								CE <= '1';
								listen_time := 0;
								if (framex = '0' and Frame = '1') then
									New_data <= '1';
								else
									New_data <= '0';
									if count = 11 then
										Q0 <= buffer0;
										Q1 <= buffer1;
										Q2 <= buffer2;
										Q3 <= buffer3;
										Q4 <= buffer4;
										Q5 <= buffer5;
										Q6 <= buffer6;
										Q7 <= buffer7;
										s <= s0;
									else
										count := count + 1;
										s <= s7;						
									end if;
								end if;
							end if;
						end if;
					when others =>
						s <= s0;
				end case;
			end if;	
		end if;
	end process test;


end Behavioral;

Could anyone help me how to read the warnings and help me identify what is wrong in my code?

Thanks in advance.

Regards,

Juan

hgleamon1 · ‎11-14-2011

Consider the following lines:

CE : out std_logic := '0'; <- here you initialise the signal to 0.

variable listen_time : natural range 0 to 274 := 0; <- declaration and initialisation of variable.

if listen_time <= 274 then <- if listen_time is less than or equal to 274. This is the entire range of the variable.

elsif listen_time > 274 then <- given the above statement, how can this ever be reached?

elsif listen_time = 274 then <- given the above statement, how can this ever be reached?

Small wonder, then, that CE is always zero. It is never assigned otherwise. Did you simulate this code?

On a small note:

test : process (CLK, RST, Frame, SDI0, SDI1, SDI2, SDI3, SDI4, SDI5, SDI6, SDI7)

You then describe a synchronous process. You only need CLK in the sensitivity list.

I do not know why you receive a resources limit warning from XST. What size device are you using? If test_src is your top level entity, you have 8 32 bit vectors as outputs. That's a lot of pins ...

Regards,

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle

juansiahaan · ‎04-16-2012

Hi there,

Thanks a lot for your reply.

I modify my previous code as follows (in my opinion, it's simpler):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity delay_sum_beamforming_src is
	PORT (CLK : in std_logic;
			RST : in std_logic;
			SDI0 : in std_logic;
			SDI1 : in std_logic;
			SDI2 : in std_logic;
			SDI3 : in std_logic;
			SDI4 : in std_logic;
			SDI5 : in std_logic;
			SDI6 : in std_logic;
			SDI7 : in std_logic;
			Frame : in std_logic;
			Q0 : out std_logic_vector (11 downto 0) := (others => '0');
			Q1 : out std_logic_vector (11 downto 0) := (others => '0');
			Q2 : out std_logic_vector (11 downto 0) := (others => '0');
			Q3 : out std_logic_vector (11 downto 0) := (others => '0');
			Q4 : out std_logic_vector (11 downto 0) := (others => '0');
			Q5 : out std_logic_vector (11 downto 0) := (others => '0');
			Q6 : out std_logic_vector (11 downto 0) := (others => '0');
			Q7 : out std_logic_vector (11 downto 0) := (others => '0');
			CE : out std_logic := '0';
			New_data : out std_logic := '0'
			);
end delay_sum_beamforming_src;

architecture Behavioral of delay_sum_beamforming_src is

--Peak detector block
COMPONENT peak_detector_src
	PORT(
		CLK : IN std_logic;
		RST : IN std_logic;
		SDI0 : IN std_logic;
		SDI1 : IN std_logic;
		SDI2 : IN std_logic;
		SDI3 : IN std_logic;
		SDI4 : IN std_logic;
		SDI5 : IN std_logic;
		SDI6 : IN std_logic;
		SDI7 : IN std_logic;
		PEAK0 : OUT std_logic;
		PEAK1 : OUT std_logic;
		PEAK2 : OUT std_logic;
		PEAK3 : OUT std_logic;
		PEAK4 : OUT std_logic;
		PEAK5 : OUT std_logic;
		PEAK6 : OUT std_logic;
		PEAK7 : OUT std_logic
		);
	END COMPONENT;

--signals for dsb
signal framex : std_logic; -- for Frame
signal enable : std_logic; -- for CE
signal buffer0 : std_logic_vector (11 downto 0) := (others => '0'); --buffers from SDI0 until SDI7
signal buffer1 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer2 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer3 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer4 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer5 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer6 : std_logic_vector (11 downto 0) := (others => '0');
signal buffer7 : std_logic_vector (11 downto 0) := (others => '0');
signal trigger0 : std_logic;-- declaration for peak detection block
signal trigger1 : std_logic;
signal trigger2 : std_logic;
signal trigger3 : std_logic;
signal trigger4 : std_logic;
signal trigger5 : std_logic;
signal trigger6 : std_logic;
signal trigger7 : std_logic;

begin
CE <= enable;

Inst_peak_detector_src: peak_detector_src PORT MAP(
		CLK => CLK,
		RST => RST,
		SDI0 => SDI0,
		SDI1 => SDI1,
		SDI2 => SDI2,
		SDI3 => SDI3,
		SDI4 => SDI4,
		SDI5 => SDI5,
		SDI6 => SDI6,
		SDI7 => SDI7,
		PEAK0 => trigger0,
		PEAK1 => trigger1,
		PEAK2 => trigger2,
		PEAK3 => trigger3,
		PEAK4 => trigger4,
		PEAK5 => trigger5,
		PEAK6 => trigger6,
		PEAK7 => trigger7
	);

	--main process
	dsb : process (CLK)
	variable count : natural range 0 to 11 := 0;
	variable listen_time : natural range 0 to 275 := 0;
	begin
		if rising_edge (CLK) then
		framex <= Frame;
			if RST = '1' then
				count := 0;
				listen_time := 0;
				New_data <= '0';
				buffer0 <= (others => '0');
				buffer1 <= (others => '0');
				buffer2 <= (others => '0');
				buffer3 <= (others => '0');
				buffer4 <= (others => '0');
				buffer5 <= (others => '0');
				buffer6 <= (others => '0');
				buffer7 <= (others => '0');		
			elsif (trigger0 = '1' or trigger1 = '1' or trigger2 = '1' or trigger3 = '1' or trigger4 = '1' or trigger5 = '1' or trigger6 = '1' or trigger7 = '1') then
				if listen_time <= 274 then
					buffer0 <= buffer0 (10 downto 0) & SDI0;
					buffer1 <= buffer1 (10 downto 0) & SDI1;
					buffer2 <= buffer2 (10 downto 0) & SDI2;
					buffer3 <= buffer3 (10 downto 0) & SDI3;
					buffer4 <= buffer4 (10 downto 0) & SDI4;
					buffer5 <= buffer5 (10 downto 0) & SDI5;
					buffer6 <= buffer6 (10 downto 0) & SDI6;
					buffer7 <= buffer7 (10 downto 0) & SDI7;
					listen_time := listen_time + 1;
				elsif listen_time > 274 then
					buffer0 <= (others => '0');
					buffer1 <= (others => '0');
					buffer2 <= (others => '0');
					buffer3 <= (others => '0');
					buffer4 <= (others => '0');
					buffer5 <= (others => '0');
					buffer6 <= (others => '0');
					buffer7 <= (others => '0');
					listen_time := 0;
				elsif listen_time = 274 then
					enable <= '1';
					listen_time :=0;
					if (framex = '0' and Frame = '1') then
						New_data <= '1';
					else
						New_data <= '0';
						if count = 11 then
							Q0 <= buffer0;
							Q1 <= buffer1;
							Q2 <= buffer2;
							Q3 <= buffer3;
							Q4 <= buffer4;
							Q5 <= buffer5;
							Q6 <= buffer6;
							Q7 <= buffer7;
						else
							count := count + 1;
						end if;
					end if;
				end if;
			end if;
		end if;
	end process dsb;
			
end Behavioral;

Based on your reply I did the following:

1. I increased my listen_time range to 275 --> thanks for telling that I was stupid enough to make a condition on all range....

2. I decreased my buffer vector into 12 --> apparently using 32 pins for 8 inputs is bad idea...I'm using SP601 evaluationkit by the way.

3. I only included CLK in the sensitivity list....--> Can you explain me why only CLK is in the list? I've read somewhere that the sensitivity list should include signals that may have changes so that the process is re-evaluated...

is there any particular rule in putting signals within the sensitivity list?

4. I used an internal signal enable to be assigned to CE --> my bad...I missed this...

After synthesizing that code, I acquire much less warnings: 208 warnings and the IOBs utilization greatly reduced...

However, the warnings are always saying that a latch has a constant value of 0, due to constant pushing (I don't know what constant pushing means...what is the meaning of that?) a latch is unconnected, etc...are there mistakes in my latest code?

The complete warnings are in the attachment.

Regards,

Juan

hgleamon1 · ‎11-14-2011

Right, let's take this one at a time:

1. Sensitivity lists.

What you say about all terms that are inputs to the process being required is true for COMBINATORIAL processes. However, in a sequential process, only the clock is required (plus any asynchronous signals like a reset. However, in your case, the reset is synchronous so you only need the clock).

2. listen_time

OK, you increased the variable by 1. Let's look at the situation where the value of listen time is important:

if listen_time <= 274 then

This is comparing the listen_time value. Less than or equal to 274. This covers 275 out of 276 possible cases of listen_time. Is this what you really want to do?

elsif listen_time > 274 then

This is an "elsif". This comparison will only be examined if the previous "if" (or "elsif") condition cannot be satisfied. Thus, this comparison wiull ONLY ever happen when listen_time is equal to 275. Is this what you really want to do?

elsif listen_time = 274 then

This is an "elsif". This comparison will only be examined if the previous "if" (or "elsif") condition cannot be satisfied. Given the previous conditions, this comparison will NEVER be reached and all logic statements following it are effectively ignored.

How do PEAKx (and hence triggerx) get asserted?

3. Warnings

You seem to get a lot of trimming warnings because a lot of code is effectively ignored by synthesiser due to the comparisons that you make. It will be easier to identify the real problem when you have corrected the logical issues that you seem to have.

Regards,

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle

juansiahaan · ‎04-16-2012

Hi Howard,

Thanks a lot for your reply...

1. Thanks for your explanation about difference between sensitivity list for combinatorial and sequential process.

2. Referring to your second point, I guess my first if statement (if listen_time <= 274) makes the last if statement (if listen_time = 274) will never be executed....to make the last statement can be considered....I made the first if statement to have only less than sign (<).

In terms of the range of the listen_time variable (0 to 275), in my opinion it's suitable because the second condition needs value higher that 274, thus 275 should be the limit...

3. I'm sorry but what do you meant by asserting the triggerx and PEAKx? what I did was only putting the other module's component and assuming that the triggerx will have the value 0 or 1 in that other module...

or am I having the wrong idea here? What I'm trying to do is that I let the decision of the 1 or 0 of the triggerx by the other module...and what I have in mind is that by mapping the other module's output to this internal signal is enough...

about the warnings, do you mean that the comparison makes the trimming executed? and if yes, why is that?

What I'm trying to do is to get input from the SDIs below the limit time that I've set and ignore the inputs (makes them 0) that come after that time limit....but the input should be higher than a certain value and I thought that process can be done in another module...if you don't mind...do you have any suggestion you can share to remove the trimming warnings?

Regards,

Juan

hgleamon1 · ‎11-14-2011

1. OK.

2. May be 275 is a good limit. I don't know - it's your code!

3. What I meant was, as I cannot see into your instantiated component, what logic controls the outputs PEAKx? What conditions are required to drive these signals?

The trimming occurs due to the comparisons because, as it currently stands, one situation is never reached so the logical statements are utterly redundant, thus the synthesiser removes them. This can then have a "knock-on" effect for other signals that depend on the removed logic.

I would reconsider recoding so that the comparisons are done in a logical order, e.g.

if (listen_time < 274) then ...

elsif (listen_time = 274) then ...

else ...

then, as the listen_time value increases so the if statements are reached in a sequential fashion. You also receive warnings related to the entire design but, as I cannot see what your submodule is doing, I can't really see why you receive all the warnings you do.

What does the synthesis report for the submodule say?

Have you tried simulating this design yet?

Regards,

Howard

----------
"That which we must learn to do, we learn by doing." - Aristotle

juansiahaan · ‎04-16-2012

Hi Howard,

Now all the warnings are gone thanks to your help...I also had instantiated with that other module that I mentioned before and still there were no warning messages generated....

Thanks again for your help,

Regards,

Juan