Synthesis

[adam123]

Hi.  According to fpga_editor the BEL names for the registers in a Spartan-6 slice are AFF, BFF, CFF, DFF and A5FF, B5FF, C5FF, D5FF.  However, if I try to use either

  // synthesis attribute BEL of my_instance is "AFF"

or

  (* BEL = "A5FF" *)

I get:

WARNING:Xst:3149 - Value "AFF" of property "BEL" is not applicable.
WARNING:Xst:3149 - Value "A5FF" of property "BEL" is not applicable.

These properties are being placed on FDRE and FDSE instances.

Is there something I should use instead?  By the way, assigning LUT BELs this way works just fine (even when assigning 5-LUTs to a specific "half" of the 6-lut).  I can't put the BEL constraints in the UCF file because xst trims a fair amount of my logic, and having INST lines in the UCF for components that were trimmed causes the rest of the tools (like map) to choke.

Thanks!

[adam123]

Hey, I just want to confirm that this is definitely a bug in xst 13.4 (WebCase doesn't like me; otherwise I'd submit it there).

Putting FF BEL constraints in the UCF file works, but that solution is fragile: small changes to the design can result in a FF getting trimmed by xst, in which case the resulting ngc won't have that instance anymore, so ngdbuild will choke with an error.

The ugly, ugly hack that I'm currently using is to put this in the UCF:

  INST "*my_ff_name" BEL=A5FF;

... because my Verilog is programmatically generated and I can tweak the instance names so that no instance name is ever a suffix of any other instance name.  But this is not a realistic solution for most users.