System Logic

[sunimal123]

Hi

I am using a xilinx sparten 3E on my board to acquire 20 digital lines with the strobe. I want to create a FIFO with this data. i've been trying IP core generator to implemnt the FIFO. My question is about setting the clock rate for the FIFO. do i need to set this as the same as the data rate? any pointers will be appreciated? Thanks.

[eteam00]

How does the FPGA logic know when a new digital input word is being presented to the FPGA?  Is there a flag or strobe or clock accompanying the data to signal that the input data is valid?

Are you taking a logic design course?  If so, have you asked your instructor for help on this question?

-- Bob Elkind

[rcingham]

The 'clock rate' is just that: the frequency of the clock applied to the clock input(s) of the FIFO.

In some systems this may be many times the rate at which data is updated.

[sunimal123]

there is a STROBE signal with data. i can run this to the FIFO to let it know that the data is valid. Clock input to the FIFO is not required then right? I am not taking any logic courses. i am just trying to brush up what i learned when i was in school.

What i am trying to do is acquire 20 data lines(these have a strobe signal)  and write that to a FIFO then transfer it to a register or memory  that way CPU can do a I/O read to access this data. any pointers will be appreciated

Thanks

Sunny 

[eteam00 · Accepted solution]

there is a STROBE signal with data. i can run this to the FIFO to let it know that the data is valid. Clock input to the FIFO is not required then right?

The STROBE can serve as the substitute for the write port clock.  Check the Spartan-3e datasheet for setup and hold time requirements at the FIFO.  The active FIFO clock edge is the rising edge, so invert the STROBE polarity if needed.

I am not taking any logic courses. i am just trying to brush up what i learned when i was in school.

If you are trying to teach yourself, you are not off to a good start.  Your first action should have been to download the FIFO user guide (UG175) and the FPGA device family datasheet (DS312).  This would be a much better example of 'teaching yourself' than posting on a user forum.

-- Bob Elkind

[sunimal123]

Hi,

If i use strobe as my write clock to the FIFO then IP CORE requires a  wr_en signal. Can i use connect vcc to this to make wr_en high all the time.

i think i am confused here. strobe is there to tell data is valid. can i use this as wr_en signal and use different clock as the FIFO clock.

Thanks,
Suni

[eteam00]

Draw a timing diagram of data, strobe, and clock.  This should help you decide whether to write to the FIFO on

• the leading edge of the strobe
• the trailing edge of the strobe
• or the clock edge (using the strobe as write enable)

-- Bob Elkind