02-01-2012 05:42 AM
For FPGA's "a lot of logic" generally depends more on the number of inputs to a gate (fan-in) than
to the actual function performed. For wide AND gates, you might get help from the carry chain
structure, but generally more inputs translates into more "levels of logic" which is where the
delay comes in.
In any case, if your signals took more than the clock period to propagate to the FIFO, you should
have had errors in the static timing report (you DO have a period constraint on the clock?).
02-01-2012 05:49 AM
Yes, there is a period constraint on the clock with 6.667 ns. I'm trying to change the design a bit since the structure with the "valid_rq" signal seems a bit awkward to me. PAR tells me that there aren't any timing constraint errors.
02-01-2012 06:13 AM
Do any of the signals used for generating wr_en come from off-chip? Remember that the
period constraint only checks paths from the Q output of one flop to the D input of another
inside the FPGA. If you have any inputs that aren't registered in the IOB you need to have
"offset in before" constraints to make sure that timing is met.
02-01-2012 06:14 AM
A 48-bit and_reduce function definitely falls within my definition of a lot of logic! I would pipeline that logic and ensure that 'wr_en' comes direct from a register.
"If it don't work in simulation, it won't work on the board."
02-01-2012 06:24 AM
@Gabor: No, neither of these signals are coming off-chip.
Regarding the 48-bit and_reduce: I'm going to alter this, indeed i've altered it right now. The problem is, that i need to count until mc_addr_gen_count_to_in is reached. But the last request should be send on mc_addr_gen_count_to_in - 1, so i've introduced the done_flag and negated valid_rq whenever done_flag is high. But i'm thinking that this isn't a good design, anyway counting only to mc_addr_gen_count_to_in - 1 seems not an option since it may happen that this last request is stalled and then it's lost.
02-01-2012 06:40 AM
As long as you pipeline everything in the write path consistently (controls and enables as well as data), it should all work, yes?
-- Bob Elkind
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