Hello:
We created a 1024x16bits FIFO to be implemented on an Spartan XC2S100-6PQ208 device. The FIFO was generated with the Core Generator from Xilinx. We are experiencing problems with the empty flag response. The FIFO Empty flag is taking too much time (ms) to be desasserted after multiple write operations have been performed (at a 20kword per second). Why could this be happening, is it possible that there is problem with core, how could external logic affect the FIFO empty flag performance?. We also ran a test on the FIFO itself by loading adn readin data manually. At these rates all FIFO features behave as they should given the slow timing, why is it affected when performing a higher frequencies? If any body can help me with this issue, I'd appreciate it.
