I have just changed an asynchronous FIFO produced by Fifo Generator 6.2 from 'Standard' to FWFT, and the result gives me a very rude simulation message (ModelSim PE 6.5f, as it happens):
# ** Failure: DRC Error : The attribute ALMOST_EMPTY_OFFSET on AFIFO36_INTERNAL is set to 8. It must be set to a value greater than (4 * roundup (WRCLK frequency / RDCLK frequency)) when AFIFO36_INTERNAL is configured in FIRST_WORD_FALL_THROUGH mode.
# Time: 120500 ps Iteration: 2 Process: /asterix_tb/video_fifo/bu2_u0_gbiv5_bi_v5_fifo_fblk_gextw_4_inst_extd_gonep_inst_prim_gfn72_sngfifo36/fifo36_exp_inst/safe_mode/prcs_read File: C:/Xilinx12.3/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd
# Break in Process prcs_read at C:/Xilinx12.3/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd line 879
# Simulation Breakpoint: Break in Process prcs_read at C:/Xilinx12.3/ISE_DS/ISE/vhdl/src/unisims/primitive/AFIFO36_INTERNAL.vhd line 879
The XCO file is:
##############################################################
#
# Xilinx Core Generator version 12.3
# Date: Mon Jun 27 12:39:59 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vfx100t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=async_fifo_8kx13
CSET data_count=false
CSET data_count_width=13
CSET disable_timing_violations=true
CSET dout_reset_value=0
CSET empty_threshold_assert_value=8
CSET empty_threshold_negate_value=9
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Builtin_FIFO
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=8190
CSET full_threshold_negate_value=8189
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=13
CSET input_depth=8192
CSET output_data_width=13
CSET output_depth=8192
CSET overflow_flag=true
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=125
CSET read_data_count=false
CSET read_data_count_width=13
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=false
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=160
CSET write_data_count=false
CSET write_data_count_width=13
# END Parameters
GENERATE
# CRC: 82072f02
I will now try to find a work-around...
EDIT: The other thing I changed was to swap the Read and Write clock frequencies, as I realise I had got them the wrong way round before.
Question: As the writing is actually always done at an effective 10MHz due to 'wr_en' being a 1-in-16 strobe, should I set "write_clock_frequency=10" instead, which will make the problem magically disappear?
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"If it don't work in simulation, it won't work on the board."
