Fifo with a non-free running wr_clk

razi.marjani · ‎06-10-2012

Hi

I need an async fifo based distribured with independent clock in my design,

the wr_clk isn,t free running.

it seems 4 first word don,t write in Fifo.

I simulate my design with structural model of fifo and problem is exist.

Is a non-free running clk is n,t suitable for Wr-Clk?

thanks

gszakacs · ‎08-14-2007

The standard "asynchronous" (dual-clock) FIFO is designed for free-running clocks. I suspect

that the data that "isn't written" is actually in the FIFO, but the flags (EMPTY, DATA_COUNT...) won't

show it because they need more write clocks to push the status through to the read clock domain.

If you have access to a free-running clock synchronous to your write signal, then use that for the

FIFO write clock. Otherwise you may need to use another approach to transfer your write data

to another free-running clock domain.

-- Gabor

razi.marjani · ‎06-10-2012

Hi

My project is about write and read to/from an ide device. I coded the UDMA protocol for these porpuse.

In read UDMA, ide device send Data to hose on falling and rising edge of a srobe.

I used strobe as wr-clk and when I want to store data to fifo I assert wr_en but strobe isn't free running.

is there another approach?

thanks

bassman59 · ‎02-25-2008

razi.marjani wrote:

Hi

My project is about write and read to/from an ide device. I coded the UDMA protocol for these porpuse.

In read UDMA, ide device send Data to hose on falling and rising edge of a srobe.

I used strobe as wr-clk and when I want to store data to fifo I assert wr_en but strobe isn't free running.

is there another approach?

thanks

Synchronize your strobe to the FPGA's system clock, and use the valid edges of the strobe to generate a write enable synchronous to the clock. Also, you probably should make sure that your data and your addresses are also synchronous to the clock.

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